From bbf8e747561f34f1be8c1940d9851c71187ae3c8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 14 Jul 2020 20:54:21 +0100 Subject: [PATCH] reduce code size by using CompOpSubsetBase for ALU and Logical --- src/soc/fu/alu/alu_input_record.py | 40 +++------------------ src/soc/fu/logical/logical_input_record.py | 42 +++------------------- 2 files changed, 8 insertions(+), 74 deletions(-) diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py index 253714e9..0b231cfd 100644 --- a/src/soc/fu/alu/alu_input_record.py +++ b/src/soc/fu/alu/alu_input_record.py @@ -1,9 +1,9 @@ -from nmigen.hdl.rec import Record, Layout - +from soc.fu.base_input_record import CompOpSubsetBase from soc.decoder.power_enums import MicrOp, Function, CryIn +from nmigen.hdl.rec import Layout -class CompALUOpSubset(Record): +class CompALUOpSubset(CompOpSubsetBase): """CompALUOpSubset a copy of the relevant subset information from Decode2Execute1Type @@ -27,37 +27,5 @@ class CompALUOpSubset(Record): ('data_len', 4), # actually used by ALU, in OP_EXTS ('insn', 32), ) + super().__init__(layout, name=name) - Record.__init__(self, Layout(layout), name=name) - - # grrr. Record does not have kwargs - self.insn_type.reset_less = True - self.fn_unit.reset_less = True - self.zero_a.reset_less = True - self.invert_a.reset_less = True - self.invert_out.reset_less = True - self.input_carry.reset_less = True - self.output_carry.reset_less = True - self.is_32bit.reset_less = True - self.is_signed.reset_less = True - self.data_len.reset_less = True - - def eq_from_execute1(self, other): - """ use this to copy in from Decode2Execute1Type - """ - res = [] - for fname, sig in self.fields.items(): - eqfrom = other.do.fields[fname] - res.append(sig.eq(eqfrom)) - return res - - def ports(self): - return [self.insn_type, - self.invert_a, - self.invert_out, - self.input_carry, - self.output_carry, - self.is_32bit, - self.is_signed, - self.data_len, - ] diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py index 7040f0e5..3e678038 100644 --- a/src/soc/fu/logical/logical_input_record.py +++ b/src/soc/fu/logical/logical_input_record.py @@ -1,9 +1,9 @@ -from nmigen.hdl.rec import Record, Layout - +from nmigen.hdl.rec import Layout from soc.decoder.power_enums import MicrOp, Function, CryIn +from soc.fu.base_input_record import CompOpSubsetBase -class CompLogicalOpSubset(Record): +class CompLogicalOpSubset(CompOpSubsetBase): """CompLogicalOpSubset a copy of the relevant subset information from Decode2Execute1Type @@ -27,38 +27,4 @@ class CompLogicalOpSubset(Record): ('data_len', 4), ('insn', 32), ) - - Record.__init__(self, Layout(layout), name=name) - - # grrr. Record does not have kwargs - self.insn_type.reset_less = True - self.fn_unit.reset_less = True - self.zero_a.reset_less = True - self.invert_a.reset_less = True - self.invert_out.reset_less = True - self.input_carry.reset_less = True - self.output_carry.reset_less = True - self.is_32bit.reset_less = True - self.is_signed.reset_less = True - self.data_len.reset_less = True - - def eq_from_execute1(self, other): - """ use this to copy in from Decode2Execute1Type - """ - res = [] - for fname, sig in self.fields.items(): - eqfrom = other.do.fields[fname] - res.append(sig.eq(eqfrom)) - return res - - def ports(self): - return [self.insn_type, - self.fn_unit, - self.invert_a, - self.invert_out, - self.input_carry, - self.output_carry, - self.is_32bit, - self.is_signed, - self.data_len, - ] + super().__init__(layout, name=name) -- 2.30.2