From bc4900835fe18ad8ab37bcff74207918c3b6780e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 22 Mar 2023 17:31:27 -0700 Subject: [PATCH] convert fmv[f/t]g to fmv[f/t]g[s][.] --- openpower/sv/int_fp_mv.mdwn | 113 +++++++++++++---------------------- openpower/sv/rfc/ls006.mdwn | 115 +++++++++++++----------------------- 2 files changed, 84 insertions(+), 144 deletions(-) diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index abebc5004..50fb1e2b7 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -248,7 +248,8 @@ fishmv f4, 0x8000 # writes +1.00390625 to f4 # Immediate Tables -Tables that are used by `fmvtg`/`fmvfg`/`fcvttg`/`fcvtfg`: +Tables that are used by +`fmvtg[s][.]`/`fmvfg[s][.]`/`fcvttg[s][.]`/`fcvtfg[s][.]`: ## `RCS` -- `Rc` and `s` @@ -289,25 +290,22 @@ Tables that are used by `fmvtg`/`fmvfg`/`fcvttg`/`fcvtfg`: These instructions perform a straight unaltered bit-level copy from one Register File to another. -## FPR to GPR move +## FPR to GPR Move -`fmvtg RT, FRB, RCS` +`fmvtg RT, FRB` +`fmvtg. RT, FRB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | RT | 0 | FRB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | RT | 0 | FRB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses - else - RT <- (FRB) + RT <- (FRB) ``` -Move a 32/64-bit float from a FPR to a GPR, just copying bits of the -IEEE 754 representation directly. This is equivalent to `stfs` followed -by `lwz` or equivalent to `stfd` followed by `ld`. As `fmvtg` is just -copying bits, `FPSCR` is not affected in any way. +Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `stfd` followed by `ld`. +As `fmvtg` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point operations. @@ -316,25 +314,22 @@ Special Registers altered: CR0 (if Rc=1) -## FPR to GPR move +## FPR to GPR Move Single -`fmvtg RT, FRB, RCS` +`fmvtgs RT, FRB` +`fmvtgs. RT, FRB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | RT | 0 | FRB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | RT | 0 | FRB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses - else - RT <- (FRB) + RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses ``` -Move a 32/64-bit float from a FPR to a GPR, just copying bits of the -IEEE 754 representation directly. This is equivalent to `stfs` followed -by `lwz` or equivalent to `stfd` followed by `ld`. As `fmvtg` is just -copying bits, `FPSCR` is not affected in any way. +Move a 32-bit float from a FPR to a GPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `stfs` followed by `lwz`. +As `fmvtgs` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point operations. @@ -343,34 +338,22 @@ Special Registers altered: CR0 (if Rc=1) -### Assembly Aliases - -| Assembly Alias | Full Instruction | -|-------------------|--------------------| -| `fmvtg RT, FRB` | `fmvtg RT, FRB, 0` | -| `fmvtg. RT, FRB` | `fmvtg RT, FRB, 1` | -| `fmvtgs RT, FRB` | `fmvtg RT, FRB, 2` | -| `fmvtgs. RT, FRB` | `fmvtg RT, FRB, 3` | - -## GPR to FPR move +## GPR to FPR Move -`fmvfg FRT, RB, RCS` +`fmvfg FRT, RB` +`fmvfg. FRT, RB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | FRT | 0 | RB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | FRT | 0 | RB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses - else - FRT <- (RB) + FRT <- (RB) ``` -move a 32/64-bit float from a GPR to a FPR, just copying bits of the IEEE -754 representation directly. This is equivalent to `stw` followed by `lfs` -or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits, -`FPSCR` is not affected in any way. +move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `std` followed by `lfd`. +As `fmvfg` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point operations. @@ -379,25 +362,22 @@ Special Registers altered: CR1 (if Rc=1) -## GPR to FPR move +## GPR to FPR Move Single -`fmvfg FRT, RB, RCS` +`fmvfgs FRT, RB` +`fmvfgs. FRT, RB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | FRT | 0 | RB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | FRT | 0 | RB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses - else - FRT <- (RB) + FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses ``` -move a 32/64-bit float from a GPR to a FPR, just copying bits of the IEEE -754 representation directly. This is equivalent to `stw` followed by `lfs` -or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits, -`FPSCR` is not affected in any way. +move a 32-bit float from a GPR to a FPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `stw` followed by `lfs`. +As `fmvfgs` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point operations. @@ -406,15 +386,6 @@ Special Registers altered: CR1 (if Rc=1) -### Assembly Aliases - -| Assembly Alias | Full Instruction | -|-------------------|--------------------| -| `fmvfg FRT, RB` | `fmvfg FRT, RB, 0` | -| `fmvfg. FRT, RB` | `fmvfg FRT, RB, 1` | -| `fmvfgs FRT, RB` | `fmvfg FRT, RB, 2` | -| `fmvfgs. FRT, RB` | `fmvfg FRT, RB, 3` | - # Conversions Unlike the move instructions diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn index 4424be97c..c007cf2fc 100644 --- a/openpower/sv/rfc/ls006.mdwn +++ b/openpower/sv/rfc/ls006.mdwn @@ -88,7 +88,8 @@ Add the following entries to: # Immediate Tables -Tables that are used by `fmvtg`/`fmvfg`/`fcvttg`/`fcvtfg`: +Tables that are used by +`fmvtg[s][.]`/`fmvfg[s][.]`/`fcvttg[s][.]`/`fcvtfg[s][.]`: ## `RCS` -- `Rc` and `s` @@ -128,25 +129,22 @@ Tables that are used by `fmvtg`/`fmvfg`/`fcvttg`/`fcvtfg`: \newpage{} -## FPR to GPR move +## FPR to GPR Move -`fmvtg RT, FRB, RCS` +`fmvtg RT, FRB` +`fmvtg. RT, FRB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | RT | 0 | FRB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | RT | 0 | FRB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses - else - RT <- (FRB) + RT <- (FRB) ``` -Move a 32/64-bit float from a FPR to a GPR, just copying bits of the -IEEE 754 representation directly. This is equivalent to `stfs` followed -by `lwz` or equivalent to `stfd` followed by `ld`. As `fmvtg` is just -copying bits, `FPSCR` is not affected in any way. +Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `stfd` followed by `ld`. +As `fmvtg` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point operations. @@ -155,30 +153,26 @@ Special Registers altered: CR0 (if Rc=1) - ---------- \newpage{} -## FPR to GPR move +## FPR to GPR Move Single -`fmvtg RT, FRB, RCS` +`fmvtgs RT, FRB` +`fmvtgs. RT, FRB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | RT | 0 | FRB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | RT | 0 | FRB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses - else - RT <- (FRB) + RT <- [0] * 32 || SINGLE((FRB)) # SINGLE since that's what stfs uses ``` -Move a 32/64-bit float from a FPR to a GPR, just copying bits of the -IEEE 754 representation directly. This is equivalent to `stfs` followed -by `lwz` or equivalent to `stfd` followed by `ld`. As `fmvtg` is just -copying bits, `FPSCR` is not affected in any way. +Move a 32-bit float from a FPR to a GPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `stfs` followed by `lwz`. +As `fmvtgs` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point operations. @@ -187,39 +181,26 @@ Special Registers altered: CR0 (if Rc=1) -### Assembly Aliases - -| Assembly Alias | Full Instruction | -|-------------------|--------------------| -| `fmvtg RT, FRB` | `fmvtg RT, FRB, 0` | -| `fmvtg. RT, FRB` | `fmvtg RT, FRB, 1` | -| `fmvtgs RT, FRB` | `fmvtg RT, FRB, 2` | -| `fmvtgs. RT, FRB` | `fmvtg RT, FRB, 3` | - - ---------- \newpage{} -## GPR to FPR move +## GPR to FPR Move -`fmvfg FRT, RB, RCS` +`fmvfg FRT, RB` +`fmvfg. FRT, RB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | FRT | 0 | RB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | FRT | 0 | RB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses - else - FRT <- (RB) + FRT <- (RB) ``` -move a 32/64-bit float from a GPR to a FPR, just copying bits of the IEEE -754 representation directly. This is equivalent to `stw` followed by `lfs` -or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits, -`FPSCR` is not affected in any way. +move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `std` followed by `lfd`. +As `fmvfg` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point operations. @@ -232,25 +213,22 @@ Special Registers altered: \newpage{} -## GPR to FPR move +## GPR to FPR Move Single -`fmvfg FRT, RB, RCS` +`fmvfgs FRT, RB` +`fmvfgs. FRT, RB` -| 0-5 | 6-10 | 11-15 | 16-20 | 21-29 | 30-31 | Form | -|-----|------|-------|-------|-------|-------|--------| -| PO | FRT | 0 | RB | XO | RCS | X-Form | +| 0-5 | 6-10 | 11-15 | 16-20 | 21-30 | 31 | Form | +|-----|------|-------|-------|-------|----|--------| +| PO | FRT | 0 | RB | XO | Rc | X-Form | ``` - if RCS[0] = 1 then # if Single mode - FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses - else - FRT <- (RB) + FRT <- DOUBLE((RB)[32:63]) # DOUBLE since that's what lfs uses ``` -move a 32/64-bit float from a GPR to a FPR, just copying bits of the IEEE -754 representation directly. This is equivalent to `stw` followed by `lfs` -or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits, -`FPSCR` is not affected in any way. +move a 32-bit float from a GPR to a FPR, just copying bits of the IEEE 754 +representation directly. This is equivalent to `stw` followed by `lfs`. +As `fmvfgs` is just copying bits, `FPSCR` is not affected in any way. Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point operations. @@ -259,15 +237,6 @@ Special Registers altered: CR1 (if Rc=1) -### Assembly Aliases - -| Assembly Alias | Full Instruction | -|-------------------|--------------------| -| `fmvfg FRT, RB` | `fmvfg FRT, RB, 0` | -| `fmvfg. FRT, RB` | `fmvfg FRT, RB, 1` | -| `fmvfgs FRT, RB` | `fmvfg FRT, RB, 2` | -| `fmvfgs. FRT, RB` | `fmvfg FRT, RB, 3` | - ---------- \newpage{} -- 2.30.2