From c13de7c60cbd63b700119d0e5f747ad4fb37f440 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 26 Mar 2023 20:50:38 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 5df704f4a..0851e021e 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -297,7 +297,8 @@ This is equivalent to `llvm.masked.compressstore.*` followed by `llvm.masked.expandload.*` -with a single instruction. +with a single instruction, but abstracted out from Load/Store and applicable +in general to any 2P instruction. This extreme power and flexibility comes down to the fact that SVP64 is not actually a Vector ISA: it is a loop-abstraction-concept that @@ -312,7 +313,7 @@ Two bits in the `SVSHAPE` [[sv/spr]] enable either "packing" or "unpacking" on the subvectors vec2/3/4. -First, llustrating a +First, illustrating a "normal" SVP64 operation with `SUBVL!=1:` (assuming no elwidth overrides), note that the VL loop is outer and the SUBVL loop inner: @@ -326,7 +327,8 @@ note that the VL loop is outer and the SUBVL loop inner: For pack/unpack (again, no elwidth overrides), note that now there is the option to swap the SUBVL and VL loop orders. -In effect the Pack/Unpack performs a Transpose of the subvector elements: +In effect the Pack/Unpack performs a Transpose of the subvector elements. +Illustrated this time with a GPR mv operation: # yield an outer-SUBVL or inner VL loop with SUBVL def index_p(outer): -- 2.30.2