From c19d74a8f7c7bb10cf3edc8f8c726eb69a86642f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 23 Sep 2021 23:55:35 +0100 Subject: [PATCH] move pc_i and svstate_i inside if self.run_hdl --- src/soc/simple/test/test_runner.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 410e6fbb..b25bc32f 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -267,9 +267,6 @@ class TestRunner(FHDLTestCase): def run_all(self): m = Module() comb = m.d.comb - pc_i = Signal(32) - svstate_i = Signal(64) - if self.microwatt_mmu: ldst_ifacetype = 'test_mmu_cache_wb' else: @@ -295,6 +292,7 @@ class TestRunner(FHDLTestCase): # StateRunner.setup_for_test() if self.run_hdl: + #hard_reset = Signal(reset_less=True) issuer = TestIssuerInternal(pspec) # use DMI RESET command instead, this does actually work though @@ -313,6 +311,9 @@ class TestRunner(FHDLTestCase): comb += intclk.eq(ClockSignal()) if self.run_hdl: + pc_i = Signal(32) + svstate_i = Signal(64) + comb += issuer.pc_i.data.eq(pc_i) comb += issuer.svstate_i.data.eq(svstate_i) -- 2.30.2