From c20a7f61310a01126862f31ba1d9d364b226cf81 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 27 Jun 2023 18:53:32 -0700 Subject: [PATCH] reformat markdown tables --- .../sv/int_fp_mv/moves_and_conversions.mdwn | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index 9010a036d..45a2d7a2c 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -243,16 +243,16 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | -|----------------------|----------------------| -| `ctfprw FRT, RB` | `ctfpr FRT, RB, 0` | -| `ctfprw. FRT, RB` | `ctfpr. FRT, RB, 0` | -| `ctfpruw FRT, RB` | `ctfpr FRT, RB, 1` | -| `ctfpruw. FRT, RB` | `ctfpr. FRT, RB, 1` | -| `ctfprd FRT, RB` | `ctfpr FRT, RB, 2` | -| `ctfprd. FRT, RB` | `ctfpr. FRT, RB, 2` | -| `ctfprud FRT, RB` | `ctfpr FRT, RB, 3` | -| `ctfprud. FRT, RB` | `ctfpr. FRT, RB, 3` | +| Assembly Alias | Full Instruction | +|--------------------|---------------------| +| `ctfprw FRT, RB` | `ctfpr FRT, RB, 0` | +| `ctfprw. FRT, RB` | `ctfpr. FRT, RB, 0` | +| `ctfpruw FRT, RB` | `ctfpr FRT, RB, 1` | +| `ctfpruw. FRT, RB` | `ctfpr. FRT, RB, 1` | +| `ctfprd FRT, RB` | `ctfpr FRT, RB, 2` | +| `ctfprd. FRT, RB` | `ctfpr. FRT, RB, 2` | +| `ctfprud FRT, RB` | `ctfpr FRT, RB, 3` | +| `ctfprud. FRT, RB` | `ctfpr. FRT, RB, 3` | ---------- @@ -312,8 +312,8 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | -|----------------------|----------------------| +| Assembly Alias | Full Instruction | +|---------------------|---------------------| | `ctfprws FRT, RB` | `ctfpr FRT, RB, 0` | | `ctfprws. FRT, RB` | `ctfpr. FRT, RB, 0` | | `ctfpruws FRT, RB` | `ctfpr FRT, RB, 1` | @@ -403,18 +403,18 @@ are all set as normal for any GPR instructions that overflow. Key for pseudo-code: -| term | result type | definition | -|---------------------------|-------------|----------------------------------------------------------------------------------------------------| -| `fp` | -- | `f32` or `f64` (or other types from SimpleV) | -| `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) | -| `uint` | -- | the unsigned integer of the same bit-width as `int` | -| `int::BITS` | `int` | the bit-width of `int` | -| `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` | -| `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` | -| `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` | -| `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` | -| `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. | -| `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` | +| term | result type | definition | +|---------------------------|-------------|-----------------------------------------------------------------------------------------------| +| `fp` | -- | `f32` or `f64` (or other types from SimpleV) | +| `int` | -- | `u32`/`u64`/`i32`/`i64` (or other types from SimpleV) | +| `uint` | -- | the unsigned integer of the same bit-width as `int` | +| `int::BITS` | `int` | the bit-width of `int` | +| `uint::MIN_VALUE` | `uint` | the minimum value `uint` can store: `0` | +| `uint::MAX_VALUE` | `uint` | the maximum value `uint` can store: `2^int::BITS - 1` | +| `int::MIN_VALUE` | `int` | the minimum value `int` can store : `-2^(int::BITS-1)` | +| `int::MAX_VALUE` | `int` | the maximum value `int` can store : `2^(int::BITS-1) - 1` | +| `int::VALUE_COUNT` | Integer | the number of different values `int` can store (`2^int::BITS`). too big to fit in `int`. | +| `rint(fp, rounding_mode)` | `fp` | rounds the floating-point value `fp` to an integer according to rounding mode `rounding_mode` |
OpenPower conversion semantics (section A.2 page 1009 (page 1035) of @@ -611,8 +611,8 @@ Special Registers altered: ### Assembly Aliases -| Assembly Alias | Full Instruction | -|---------------------------|----------------------------| +| Assembly Alias | Full Instruction | +|--------------------------|---------------------------| | `cffprw RT, FRB, CVM` | `cffpr RT, FRB, CVM, 0` | | `cffprw. RT, FRB, CVM` | `cffpr. RT, FRB, CVM, 0` | | `cffprwo RT, FRB, CVM` | `cffpro RT, FRB, CVM, 0` | -- 2.30.2