From c2bd40b6f3e70022a7a72d1fada76a0daff61ddc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 16 May 2019 16:41:53 +0100 Subject: [PATCH] reorg instr test issue --- src/experiment/score6600.py | 76 ++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 39 deletions(-) diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 116bf96a..591fb794 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -362,51 +362,49 @@ def scoreboard_sim(dut, alusim): yield + instrs = [] if False: - yield from int_instr(dut, alusim, IADD, 4, 3, 5) - yield from print_reg(dut, [3,4,5]) - yield - yield from int_instr(dut, alusim, IADD, 5, 2, 5) - yield from print_reg(dut, [3,4,5]) - yield - yield from int_instr(dut, alusim, ISUB, 5, 1, 3) - yield from print_reg(dut, [3,4,5]) - yield - for i in range(len(dut.int_insn_i)): - yield dut.int_insn_i[i].eq(0) - yield from print_reg(dut, [3,4,5]) - yield - yield from print_reg(dut, [3,4,5]) - yield - yield from print_reg(dut, [3,4,5]) - yield + for i in range(2): + src1 = randint(1, dut.n_regs-1) + src2 = randint(1, dut.n_regs-1) + while True: + dest = randint(1, dut.n_regs-1) + break + if dest not in [src1, src2]: + break + #src1 = 2 + #src2 = 3 + #dest = 2 - yield from alusim.check(dut) + op = randint(0, 1) + op = i % 2 + instrs.append((src1, src2, dest, op)) - for i in range(5): - src1 = randint(1, dut.n_regs-1) - src2 = randint(1, dut.n_regs-1) - while True: - dest = randint(1, dut.n_regs-1) - break - if dest not in [src1, src2]: - break - #src1 = 2 - #src2 = 3 - #dest = 2 + if False: + instrs.append((2, 3, 3, 0)) + instrs.append((5, 3, 3, 1)) + + if True: + instrs.append((7, 2, 6, 1)) + instrs.append((3, 7, 1, 1)) + instrs.append((2, 2, 3, 1)) + + for i, (src1, src2, dest, op) in enumerate(instrs): - op = randint(0, 1) - #op = i % 2 - print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest)) + print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest)) yield from int_instr(dut, alusim, op, src1, src2, dest) yield from print_reg(dut, [3,4,5]) - yield - yield from print_reg(dut, [3,4,5]) - for i in range(len(dut.int_insn_i)): - yield dut.int_insn_i[i].eq(0) - yield - yield - + while True: + yield + issue_o = yield dut.issue_o + if issue_o: + yield from print_reg(dut, [3,4,5]) + for i in range(len(dut.int_insn_i)): + yield dut.int_insn_i[i].eq(0) + break + print ("busy",) + yield from print_reg(dut, [3,4,5]) + yield yield yield from print_reg(dut, [3,4,5]) -- 2.30.2