From c66087216aba6428fea769f14ad7f994a846de62 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 Jun 2018 05:52:19 +0100 Subject: [PATCH] reorg --- simple_v_extension/simple_v_chennai_2018.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 8cec8922e..09019e992 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -720,7 +720,7 @@ loop: \item An extra pipeline phase almost certainly essential\\ for fast low-latency implementations\vspace{4pt} \item With zeroing off, skipping non-predicated elements is hard:\\ - it is however an optimisation (and could be skipped).\vspace{4pt} + it is however an optimisation (and need not be done).\vspace{4pt} \item Setting up the Register/Predication tables (interpreting the\\ CSR key-value stores) might be a bit complex to optimise (any change to a CSR key-value entry needs to redo the table) -- 2.30.2