From c95d11062975635395594d2c5682ce59d1ffb145 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 Jun 2018 05:26:26 +0100 Subject: [PATCH] reorg --- simple_v_extension/simple_v_chennai_2018.tex | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index c156ed4ad..9fe437185 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -695,9 +695,11 @@ loop: \frame{\frametitle{Under consideration} \begin{itemize} - \item Is C.FNE actually needed? Should it be added if it is? + \item Should future extra bank be included now? + \item How many Register and Predication CSRs should there be?\\ + (and how many in RV32E) + \item How many in M-Mode (for doing context-switch)? \item Should use of registers be allowed to "wrap" (x30 x31 x1 x2)? - \item Can VSELECT be removed? (it's really complex) \item Can CLIP be done as a CSR (mode, like elwidth) \item SIMD saturation (etc.) also set as a mode? \item Include src1/src2 predication on Comparison Ops?\\ -- 2.30.2