From c9ae3ffaf2cd01599b254f60f9c8b47c6f2ed5d8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 15 Jul 2020 14:21:23 +0100 Subject: [PATCH] use case statement in PowerDecode2 --- src/soc/decoder/power_decoder2.py | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 06bdf14e..3f5686ba 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -368,15 +368,14 @@ class DecodeOut2(Elaboratable): # B, BC or BCREG: potential implicit register (LR) output # these give bl, bcl, bclrl, etc. op = self.dec.op - with m.If((op.internal_op == MicrOp.OP_BC) | - (op.internal_op == MicrOp.OP_B) | - (op.internal_op == MicrOp.OP_BCREG)): - with m.If(self.lk): # "link" mode - comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR - comb += self.fast_out.ok.eq(1) + with m.Switch(op.internal_op): + with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG): + with m.If(self.lk): # "link" mode + comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR + comb += self.fast_out.ok.eq(1) - # RFID 2nd spr (fast) - with m.If(op.internal_op == MicrOp.OP_RFID): + # RFID 2nd spr (fast) + with m.Case(MicrOp.OP_RFID): comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1 comb += self.fast_out.ok.eq(1) -- 2.30.2