From cbcce1ae071cf6795e1ca0914c16342680163e02 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 26 Nov 2018 01:01:03 +0000 Subject: [PATCH] start converting get_fetch_action --- cpu.py | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/cpu.py b/cpu.py index d345a00..c73c425 100644 --- a/cpu.py +++ b/cpu.py @@ -218,12 +218,21 @@ class CPU(Module): branch_taken, misaligned_jump_target, csr_op_is_valid): c = {} + c["default"] = ft.action.eq(FA.default) # XXX hmm, should be 32'XXXXXXXX + c[FOS.empty] = ft.action.eq(FA.default) + c[FOS.trap] = ft.action.eq(FA.ack_trap) + + ifs = If((dc.act & DA.trap_illegal_instruction) != 0, + ft.action.eq(FA.error_trap) + ).Elif((dc.act & DA.trap_ecall_ebreak) != 0, + ft.action.eq(FA.noerror_trap) + ) + + c[FOS.valid] = ifs + + return Case(ft.output_state, c) + """ - case(fetch_output_state) - `fetch_output_state_empty: - get_fetch_action = `fetch_action_default; - `fetch_output_state_trap: - get_fetch_action = `fetch_action_ack_trap; `fetch_output_state_valid: begin if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin get_fetch_action = `fetch_action_error_trap; @@ -453,7 +462,7 @@ class CPU(Module): self.comb += loaded_value.eq(Cat(b0, b1, b2)) self.comb += mi.rw_active.eq(~self.reset - & (ft.output_state == fetch_output_state_valid) + & (ft.output_state == FOS.valid) & ~load_store_misaligned & ((dc.act & (DA.load | DA.store)) != 0)) @@ -524,6 +533,10 @@ class CPU(Module): csr_op_is_valid = Signal() + self.comb += self.get_fetch_action(ft, dc, + load_store_misaligned, mi, + branch_taken, misaligned_jump_target, + csr_op_is_valid) if __name__ == "__main__": example = CPU() print(verilog.convert(example, -- 2.30.2