From cc8a0511f0b3424d9948a8ad42f9167a0d105c32 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sat, 8 Jan 2022 14:30:25 +0100 Subject: [PATCH] add function test_pi_ld_misalign --- src/soc/experiment/test/test_loadstore1.py | 25 ++++++++++++++-------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py index 5e629268..8cf2e119 100644 --- a/src/soc/experiment/test/test_loadstore1.py +++ b/src/soc/experiment/test/test_loadstore1.py @@ -516,6 +516,16 @@ def _test_loadstore1_microwatt_mmu_bin_test2(dut, mem): wbget.stop = True +def test_pi_ld_misalign(pi,addr,data_len,msr): + for i in range(0,data_len): + ld_data, exctype, exc = yield from pi_ld(pi, addr+i, data_len, msr=msr) + yield + if i == 0: + assert exc==None + print("MISALIGN: test_pi_ld_misalign returned",hex(ld_data)) + else: + assert exc.alignment == 1 + def _test_loadstore1_misalign(dut, mem): mmu = dut.submodules.mmu pi = dut.submodules.ldst.pi @@ -526,16 +536,10 @@ def _test_loadstore1_misalign(dut, mem): yield mmu.rin.pid.eq(0x1) # set PID=1 #yield - addr = 0 #TODO - msr = MSRSpec(pr=1, dr=1, sf=1) + addr = 1 + msr = MSRSpec(pr=0, dr=0, sf=1) - #print("=== alignment error (ld:0) ===") - - ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr) - #print("ld_data after mmu.bin test2") - #print(ld_data) - #assert ld_data == 0x0000000badc0ffee - #assert exctype is None + yield from test_pi_ld_misalign(pi,0,8,msr) wbget.stop = True @@ -897,6 +901,9 @@ def test_loadstore1_misalign(): sim = Simulator(m) sim.add_clock(1e-6) + ###########1122334455667788 + mem[0] = 0x0102030405060708 + sim.add_sync_process(wrap(_test_loadstore1_misalign(m, mem))) sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem))) with sim.write_vcd('test_loadstore1_misalign.vcd'): -- 2.30.2