From cda3729febe9de32b9aa21d7bd3b8401f8b51f93 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 Jun 2018 10:46:41 +0100 Subject: [PATCH] update --- pinmux/pinmux_chennai_2018.tex | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex index 4e7c3c49d..20534e3ef 100644 --- a/pinmux/pinmux_chennai_2018.tex +++ b/pinmux/pinmux_chennai_2018.tex @@ -68,10 +68,11 @@ are actual available pins (48 to 500), the required chip package is far less costly and the chip more desirable\vspace{4pt} \item What? A many-to-many dynamically-configureable router of - I/O functions to I/O pins\vspace{4pt} - \item \bf{Note: actual muxing is deceptively simple, but like - a DRAM cell it's actually about the ancillaries / extras} + I/O functions to I/O pins \end{itemize} + \bf{Note: actual muxing is deceptively simple, but like a DRAM cell + it's actually about the extras (routing, docs, specs etc).\\ + Just as DRAM Cell != DDR3/4, Muxer Cell != Pinmux} } -- 2.30.2