From d0eb12ead2cb6b3f64eec5e7c08e831826ea96f3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 Dec 2023 14:46:01 +0000 Subject: [PATCH] add words to describe first few instructions, bug #672 popspopcount --- openpower/sv/cookbook/pospopcnt.mdwn | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/openpower/sv/cookbook/pospopcnt.mdwn b/openpower/sv/cookbook/pospopcnt.mdwn index f8b46d378..9a2d619f6 100644 --- a/openpower/sv/cookbook/pospopcnt.mdwn +++ b/openpower/sv/cookbook/pospopcnt.mdwn @@ -57,12 +57,30 @@ bit-position, of an array of input values. # Walkthrough of the assembler +Firstly the CTR (Counter) SPR is set up, and is key to looping +as outlined further, below + ``` mtspr 9, 3" # move r3 to CTR ``` +The Vector Length, which is limited to 8 (MVL - Maximum +Vector Length) is set up. A special "CTR" Mode is used +which automatically uses the CTR SPR rather than register +RA. (*Note that RA is set to zero to indicate this, because there is +limited encoding space. See [[openpower/sv/setvl]] instruction +specification for details)*. + +The result of this instruction is that if CTR is greater than +8, VL is set to 8. If however CTR is less than or equal to 8, +then VL is set to CTR. Additionally, a copy of VL is placed +into RT (r3 in this case), which again is necessary as part +of the limited encoding space but in some cases (not here) +this is desirable, and avoids a `mfspr` instruction to take +a copy of VL into a GPR. + ``` -# VL = MIN(CTR,MAXVL=8), Rc=1 (CR0 set if CTR ends) +# VL = MIN(CTR,MAXVL=8) setvl 3,0,8,0,1,1" # set MVL=8, VL=MIN(MVL,CTR) ``` -- 2.30.2