From d32bef88b8235eec4dbfc1c921b4837fda30c899 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 3 Jun 2018 07:22:21 +0100 Subject: [PATCH] add images --- simple_v_extension/simple_v_chennai_2018.tex | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 05cdc3eaa..a3fa9161e 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -313,10 +313,12 @@ for (int i = 0; i < VL; ++i) \frame{\frametitle{Why are overlaps allowed in Regfiles?} \begin{itemize} - \item Same register(s) can have multiple "interpretations"\vspace{6pt} - \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{6pt} - \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV)\vspace{6pt} - \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\vspace{6pt} + \item Same register(s) can have multiple "interpretations" + \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops + \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV:\\ + GREV @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8) + \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\\ + (BEXT/BDEP @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8) \item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt} \end{itemize} Note:\vspace{10pt} -- 2.30.2