From d5b08ba4b0ee2fd2d23246fd456e633d8cc2264d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 21:05:42 +0100 Subject: [PATCH] rename PLL pins to match LIP6.fr PLL --- libresoc/core.py | 6 +++--- libresoc/ls180.py | 4 ++-- ls180soc.py | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/libresoc/core.py b/libresoc/core.py index 0146511..c305d02 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -272,10 +272,10 @@ class LibreSoC(CPU): if "ls180" in variant and "pll" not in variant: self.pll_18_o = Signal() self.clk_sel = Signal(2) - self.pll_lck_o = Signal() - self.cpu_params['i_clk_sel_i'] = self.clk_sel + self.pll_ana_o = Signal() + self.cpu_params['i_clk__i'] = self.clk_sel self.cpu_params['o_pll_18_o'] = self.pll_18_o - self.cpu_params['o_pll_lck_o'] = self.pll_lck_o + self.cpu_params['o_vco_test_ana_o'] = self.pll_ana_o # add wishbone buses to cpu params self.cpu_params.update(make_wb_bus("ibus", ibus, True)) diff --git a/libresoc/ls180.py b/libresoc/ls180.py index ab8fb33..a03eef9 100644 --- a/libresoc/ls180.py +++ b/libresoc/ls180.py @@ -57,8 +57,8 @@ def io(): ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")), ("sys_rst", 0, Pins("R1"), IOStandard("LVCMOS33")), ("sys_clksel_i", 0, Pins("R1 R2"), IOStandard("LVCMOS33")), - ("sys_pll_18_o", 0, Pins("R1"), IOStandard("LVCMOS33")), - ("sys_pll_lck_o", 0, Pins("R1"), IOStandard("LVCMOS33")), + ("sys_pll_testout_o", 0, Pins("R1"), IOStandard("LVCMOS33")), + ("sys_pll_vco_o", 0, Pins("R1"), IOStandard("LVCMOS33")), # JTAG0: 4 pins ("jtag", 0, diff --git a/ls180soc.py b/ls180soc.py index acf2e58..d1d8dfe 100755 --- a/ls180soc.py +++ b/ls180soc.py @@ -427,12 +427,12 @@ class LibreSoCSim(SoCCore): if hasattr(self.cpu, "clk_sel"): # PLL/Clock Select clksel_i = platform.request("sys_clksel_i") - pll18_o = platform.request("sys_pll_18_o") - pll_lck_o = platform.request("sys_pll_lck_o") + pll18_o = platform.request("sys_pll_testout_o") + pll_ana_o = platform.request("sys_pll_vco_o") self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from PLL - self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag + self.comb += pll_ana_o.eq(self.cpu.pll_ana_o) # PLL lock flag #ram_init = [] -- 2.30.2