From d7f305474f31673c8c08445c0c7d9bd07f31a377 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jun 2018 02:32:23 +0100
Subject: [PATCH] add example code

---
 simple_v_extension/simple_v_chennai_2018.tex | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 32b66a094..0d4f43c3d 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -667,6 +667,8 @@ loop:
 
  \begin{itemize}
    \item Actually about parallelism, not Vectors (or SIMD) per se
+   \item Only actually needs 3 actual instructions plus CSRs\\
+         (RVV - and "standard" SIMD - require ISA duplication)
    \item Designed for flexibility (graded levels of complexity)
    \item Huge range of implementor freedom
    \item Fits RISC-V ethos: achieve more with less
-- 
2.30.2