From ddecee2047cfc33ae4e2834e9371d245dcbc0859 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 18 May 2018 14:25:23 +0100 Subject: [PATCH] note that VSETVL and MXAVECTORDEPTH have to be 15 for RV32E and 31 for RV32 or RV64 --- simple_v_extension.mdwn | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 13ab51006..8131a888d 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -608,6 +608,11 @@ XLEN bits. The second minor change is that when VSETVL is requested to be stored into x0, it is *ignored* silently. +Unlike RVV, implementors *must* provide pseudo-parallelism (using sequential +loops in hardware) if actual hardware-parallelism in the ALUs is not deployed. +A hybrid is also permitted (as used in Broadcom's VideoCore-IV) however this +must be *entirely* transparent to the ISA. + ## Branch Instruction: Branch operations use standard RV opcodes that are reinterpreted to be -- 2.30.2