From eea5f31aa48e2383e9d51fc5c1536d4fa2c16459 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 06:40:10 +0100 Subject: [PATCH] add lcd clock sync --- src/bsv/bsv_lib/soc_template.bsv | 9 ++++++--- src/bsv/peripheral_gen/base.py | 25 ++++++++++++++++++++----- src/bsv/peripheral_gen/rgbttl.py | 26 ++++++++++++++++++++++++++ src/bsv/pinmux_generator.py | 4 +++- 4 files changed, 55 insertions(+), 9 deletions(-) diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index c722604..01a05d3 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -147,11 +147,14 @@ package socgen; Ifc_vme_top vme <-mkvme_top(); `endif Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals( - core_clock, core_reset, uart_clock, - uart_reset, clocked_by slow_clock , - reset_by slow_reset + core_clock, core_reset, + uart_clock, uart_reset, + clocked_by slow_clock, reset_by slow_reset `ifdef PWM_AXI4Lite , ext_pwm_clock `endif ); + // clock sync mkConnections +{12} + // Fabric AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves, `PADDR, `DATA,`USERSPACE) diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index a79f6cf..92c41d6 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -227,12 +227,15 @@ else""" sync, n)) return ret - def mk_clk_con(self, name, count): + def _mk_clk_con(self, name, count, ctype): ret = [] ck = self.get_clock_reset(name, count) if ck == PBase.get_clock_reset(self, name, count): return '' - spc = "sp_clock, sp_reset" + if ctype == 'slow': + spc = "sp_clock, sp_reset" + else: + spc = "fast_clock, fast_reset" template = """\ Ifc_sync#({0}) {1}_sync <-mksyncconnection( {2}, {3});""" @@ -241,6 +244,9 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( pname = p['name'] n = name if typ == 'out' or typ == 'inout': + fname = self.pinname_out(pname) + if not fname: + continue if not n.startswith('gpio'): # XXX EURGH! horrible hack n_ = "{0}{1}".format(n, count) else: @@ -248,6 +254,9 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( n_ = '{0}_{1}'.format(n_, pname) ret.append(template.format("Bit#(1)", n_, ck, spc)) if typ == 'in' or typ == 'inout': + fname = self.pinname_in(pname) + if not fname: + continue #fname = self.pinname_in(pname) n_ = "{0}{1}".format(n, count) n_ = '{0}_{1}'.format(n_, pname) @@ -449,7 +458,7 @@ class PeripheralIface(object): 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule', 'mkfast_peripheral', 'mk_plic', 'mk_ext_ifacedef', - 'mk_clk_con', 'mk_ext_ifacedef', + '_mk_clk_con', 'mk_ext_ifacedef', 'mk_connection', 'mk_cellconn', '_mk_pincon']: fn = CallFn(self, fname) setattr(self, fname, types.MethodType(fn, self)) @@ -792,13 +801,19 @@ class PeripheralInterfaces(object): def mk_sloirqsdef(self): return " `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs) - def mk_clk_con(self): + def mk_fastclk_con(self): + return self._mk_clk_con("fast") + + def mk_slowclk_con(self): + return self._mk_clk_con("slow") + + def _mk_clk_con(self, ctype): ret = [] for (name, count) in self.ifacecount: for i in range(count): if self.is_on_fastbus(name, i): continue - txt = self.data[name].mk_clk_con(name, i) + txt = self.data[name]._mk_clk_con(name, i, ctype) ret.append(txt) return '\n'.join(li(list(filter(None, ret)), 8)) diff --git a/src/bsv/peripheral_gen/rgbttl.py b/src/bsv/peripheral_gen/rgbttl.py index 53bffa3..ad1027e 100644 --- a/src/bsv/peripheral_gen/rgbttl.py +++ b/src/bsv/peripheral_gen/rgbttl.py @@ -24,6 +24,9 @@ class rgbttl(PBase): return pname return '' + def get_clock_reset(self, name, count): + return "slow_clock, slow_reset" + def _mk_pincon(self, name, count, ptyp): ret = [PBase._mk_pincon(self, name, count, ptyp)] if ptyp == 'fast': @@ -39,3 +42,26 @@ class rgbttl(PBase): ret += self._mk_actual_connection('out', name, count, 'out', ptype, ps_, n, ptype) return '\n'.join(ret) + + def _mk_clk_con(self, name, count, ctype): + ret = [PBase._mk_clk_con(self, name, count, ctype)] + ck = self.get_clock_reset(name, count) + if ck == PBase.get_clock_reset(self, name, count): + return ret + if ctype == 'slow': + spc = "sp_clock, sp_reset" + else: + spc = "fast_clock, fast_reset" + template = """\ +Ifc_sync#({0}) {1}_sync <-mksyncconnection( + {2}, {3});""" + + # one pin, data_out, might as well hard-code it + typ = 'out' + pname = 'data_out' + n = name + n_ = "{0}{1}".format(n, count) + n_ = '{0}_{1}'.format(n_, pname) + sz = len(self.peripheral.pinspecs) - 4 # subtract CK, DE, HS, VS + ret.append(template.format("Bit#(%d)" % sz, n_, ck, spc)) + return '\n'.join(ret) diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 0884239..87326a7 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -121,7 +121,7 @@ def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells): numsloirqs = ifaces.mk_sloirqsdef() ifacedef = ifaces.mk_ext_ifacedef() ifacedef = ifaces.mk_ext_ifacedef() - clockcon = ifaces.mk_clk_con() + clockcon = ifaces.mk_slowclk_con() with open(slow, "w") as bsv_file: with open(slowt) as f: @@ -160,6 +160,7 @@ def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells): ifacedef = ifaces.mk_ext_ifacedef() dma = ifaces.mk_dma_irq() num_dmachannels = ifaces.num_dmachannels() + clockcon = ifaces.mk_fastclk_con() with open(soc, "w") as bsv_file: with open(soct) as f: @@ -168,6 +169,7 @@ def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells): slavedecl, mastdecl, mkcon, inst, dma, num_dmachannels, pincon, regdef, fnaddrmap, + clockcon, )) with open(fastmf, "w") as bsv_file: -- 2.30.2