From f088bd386d7ca8b4da206d5e81bdaad9dd4c6284 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 5 Feb 2024 13:57:03 +0000 Subject: [PATCH] bug 676: tidy up pseudocode --- src/openpower/decoder/isa/test_caller_svp64_maxloc.py | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py index 61a4074b..1395d3fb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py @@ -82,26 +82,21 @@ class DDFFirstTestCase(FHDLTestCase): # VL = MIN(CTR,MAXVL=4) "mtcrf 255,0", # clear CR entirely "setvl 2,0,4,0,1,1", # set MVL=4, VL=MIN(MVL,CTR) - # load VL bytes (update r4 addr) but compressed (dw=8) - #"addi 6, 0, 0", # initialise r6 to zero - #"sv.lbzu/pi/dw=8 *6, 1(4)", # should be /lf here as well # while (im): "sv.minmax./ff=le/m=ge 4, *10, 4, 1", # uses r4 as accumulator + #"crternlogi 0,1,2,127" # test greater/equal or VL=0 "cror 0,1,0", # test for greater or equal, or VL=0 "cror 0,2,0", # test for greater or equal, or VL=0 "sv.creqv *19,*16,*16", # set mask on already-tested - "sv.crand *19,*19,0", # clear if CR0=0 + "sv.crand *19,*19,0", # clear if CR0=0 "sv.svstep/mr/m=so 1, 0, 6, 1", # svstep: get vector dststep "sv.creqv *16,*16,*16", # set mask on already-tested - #"sv.addi/dm=1<r4 (and dec CTR) ]) lst = list(lst) -- 2.30.2