From f202152c8467afc84e9377b5e8f224eb8a9784e6 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 15:27:19 +0100
Subject: [PATCH] rename FPModBase* to PipeModBase*

---
 src/ieee754/fclass/fclass.py          | 4 ++--
 src/ieee754/fcvt/downsize.py          | 4 ++--
 src/ieee754/fcvt/int2float.py         | 4 ++--
 src/ieee754/fcvt/upsize.py            | 4 ++--
 src/ieee754/fpadd/add0.py             | 4 ++--
 src/ieee754/fpadd/add1.py             | 4 ++--
 src/ieee754/fpadd/addstages.py        | 4 ++--
 src/ieee754/fpadd/align.py            | 4 ++--
 src/ieee754/fpadd/specialcases.py     | 6 +++---
 src/ieee754/fpcommon/corrections.py   | 4 ++--
 src/ieee754/fpcommon/denorm.py        | 4 ++--
 src/ieee754/fpcommon/normtopack.py    | 4 ++--
 src/ieee754/fpcommon/pack.py          | 4 ++--
 src/ieee754/fpcommon/postnormalise.py | 4 ++--
 src/ieee754/fpcommon/roundz.py        | 4 ++--
 src/ieee754/fpdiv/div0.py             | 4 ++--
 src/ieee754/fpdiv/div2.py             | 4 ++--
 src/ieee754/fpdiv/divstages.py        | 8 ++++----
 src/ieee754/fpdiv/specialcases.py     | 6 +++---
 src/ieee754/fpmul/align.py            | 4 ++--
 src/ieee754/fpmul/mul0.py             | 4 ++--
 src/ieee754/fpmul/mul1.py             | 4 ++--
 src/ieee754/fpmul/mulstages.py        | 4 ++--
 src/ieee754/fpmul/specialcases.py     | 6 +++---
 src/nmutil/pipemodbase.py             | 8 ++++----
 25 files changed, 57 insertions(+), 57 deletions(-)

diff --git a/src/ieee754/fclass/fclass.py b/src/ieee754/fclass/fclass.py
index e3b7ff4c..09b5d478 100644
--- a/src/ieee754/fclass/fclass.py
+++ b/src/ieee754/fclass/fclass.py
@@ -3,13 +3,13 @@
 
 from nmigen import Module, Signal, Cat
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPClassMod(FPModBase):
+class FPClassMod(PipeModBase):
     """ obtains floating point information (zero, nan, inf etc.)
     """
     def __init__(self, in_pspec, out_pspec):
diff --git a/src/ieee754/fcvt/downsize.py b/src/ieee754/fcvt/downsize.py
index 3561f197..4a0dc822 100644
--- a/src/ieee754/fcvt/downsize.py
+++ b/src/ieee754/fcvt/downsize.py
@@ -4,7 +4,7 @@
 from nmigen import Module, Signal, Const
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.msbhigh import FPMSBHigh
@@ -13,7 +13,7 @@ from ieee754.fpcommon.exphigh import FPEXPHigh
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTDownConvertMod(FPModBase):
+class FPCVTDownConvertMod(PipeModBase):
     """ FP down-conversion (higher to lower bitwidth)
     """
     def __init__(self, in_pspec, out_pspec):
diff --git a/src/ieee754/fcvt/int2float.py b/src/ieee754/fcvt/int2float.py
index 4f559101..96c6309f 100644
--- a/src/ieee754/fcvt/int2float.py
+++ b/src/ieee754/fcvt/int2float.py
@@ -4,7 +4,7 @@
 from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.msbhigh import FPMSBHigh
@@ -12,7 +12,7 @@ from ieee754.fpcommon.msbhigh import FPMSBHigh
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTIntToFloatMod(FPModBase):
+class FPCVTIntToFloatMod(PipeModBase):
     """ FP integer conversion: copes with 16/32/64 int to 16/32/64 fp.
 
         self.ctx.i.op & 0x1 == 0x1 : SIGNED int
diff --git a/src/ieee754/fcvt/upsize.py b/src/ieee754/fcvt/upsize.py
index 483ddbbc..e225a2af 100644
--- a/src/ieee754/fcvt/upsize.py
+++ b/src/ieee754/fcvt/upsize.py
@@ -8,13 +8,13 @@ import functools
 from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTUpConvertMod(FPModBase):
+class FPCVTUpConvertMod(PipeModBase):
     """ FP up-conversion (lower to higher bitwidth)
     """
     def __init__(self, in_pspec, out_pspec):
diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index 0a77855b..fd908879 100644
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -7,7 +7,7 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 
 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
 from ieee754.fpcommon.denorm import FPSCData
@@ -30,7 +30,7 @@ class FPAddStage0Data:
                 self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
 
 
-class FPAddStage0Mod(FPModBase):
+class FPAddStage0Mod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "add0")
diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py
index 9004be8f..4b92ad1a 100644
--- a/src/ieee754/fpadd/add1.py
+++ b/src/ieee754/fpadd/add1.py
@@ -8,12 +8,12 @@ from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 from math import log
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpadd.add0 import FPAddStage0Data
 
 
-class FPAddStage1Mod(FPModBase):
+class FPAddStage1Mod(PipeModBase):
     """ Second stage of add: preparation for normalisation.
         detects when tot sum is too big (tot[27] is kinda a carry bit)
     """
diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py
index b62d6d20..d24a5c14 100644
--- a/src/ieee754/fpadd/addstages.py
+++ b/src/ieee754/fpadd/addstages.py
@@ -4,14 +4,14 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 """
 
-from nmutil.pipemodbase import FPModBaseChain
+from nmutil.pipemodbase import PipeModBaseChain
 
 from ieee754.fpadd.align import FPAddAlignSingleMod
 from ieee754.fpadd.add0 import FPAddStage0Mod
 from ieee754.fpadd.add1 import FPAddStage1Mod
 
 
-class FPAddAlignSingleAdd(FPModBaseChain):
+class FPAddAlignSingleAdd(PipeModBaseChain):
 
     def get_chain(self):
         # chain AddAlignSingle, AddStage0 and AddStage1
diff --git a/src/ieee754/fpadd/align.py b/src/ieee754/fpadd/align.py
index 0cfc38d0..7bdf1605 100644
--- a/src/ieee754/fpadd/align.py
+++ b/src/ieee754/fpadd/align.py
@@ -5,7 +5,7 @@
 from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.fpbase import MultiShiftRMerge
 from ieee754.fpcommon.denorm import FPSCData
@@ -71,7 +71,7 @@ class FPAddAlignMultiMod:
         return m
 
 
-class FPAddAlignSingleMod(FPModBase):
+class FPAddAlignSingleMod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "align")
diff --git a/src/ieee754/fpadd/specialcases.py b/src/ieee754/fpadd/specialcases.py
index c11832dc..68cad890 100644
--- a/src/ieee754/fpadd/specialcases.py
+++ b/src/ieee754/fpadd/specialcases.py
@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Cat, Const
 from nmigen.cli import main, verilog
 from math import log
 
-from nmutil.pipemodbase import FPModBase, FPModBaseChain
+from nmutil.pipemodbase import PipeModBase, PipeModBaseChain
 from ieee754.fpcommon.fpbase import FPNumDecode
 
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
@@ -14,7 +14,7 @@ from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
 
 
-class FPAddSpecialCasesMod(FPModBase):
+class FPAddSpecialCasesMod(PipeModBase):
     """ special cases: NaNs, infs, zeros, denormalised
         NOTE: some of these are unique to add.  see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
@@ -129,7 +129,7 @@ class FPAddSpecialCasesMod(FPModBase):
         return m
 
 
-class FPAddSpecialCasesDeNorm(FPModBaseChain):
+class FPAddSpecialCasesDeNorm(PipeModBaseChain):
     """ special cases chain
     """
 
diff --git a/src/ieee754/fpcommon/corrections.py b/src/ieee754/fpcommon/corrections.py
index 2ac65d79..3a069167 100644
--- a/src/ieee754/fpcommon/corrections.py
+++ b/src/ieee754/fpcommon/corrections.py
@@ -5,12 +5,12 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBase
 from ieee754.fpcommon.roundz import FPRoundData
 
 
-class FPCorrectionsMod(FPModBase):
+class FPCorrectionsMod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "corrections")
diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py
index 8210c019..52bae10a 100644
--- a/src/ieee754/fpcommon/denorm.py
+++ b/src/ieee754/fpcommon/denorm.py
@@ -6,7 +6,7 @@ from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 from math import log
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.fpbase import FPNumBase
 from ieee754.fpcommon.getop import FPPipeContext
@@ -42,7 +42,7 @@ class FPSCData:
         return ret
 
 
-class FPAddDeNormMod(FPModBase):
+class FPAddDeNormMod(PipeModBase):
 
     def __init__(self, pspec, m_extra):
         self.m_extra = m_extra
diff --git a/src/ieee754/fpcommon/normtopack.py b/src/ieee754/fpcommon/normtopack.py
index 33459a36..003516c5 100644
--- a/src/ieee754/fpcommon/normtopack.py
+++ b/src/ieee754/fpcommon/normtopack.py
@@ -4,14 +4,14 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 """
 
-from nmutil.pipemodbase import FPModBaseChain
+from nmutil.pipemodbase import PipeModBaseChain
 from ieee754.fpcommon.postnormalise import FPNorm1ModSingle
 from ieee754.fpcommon.roundz import FPRoundMod
 from ieee754.fpcommon.corrections import FPCorrectionsMod
 from ieee754.fpcommon.pack import FPPackMod
 
 
-class FPNormToPack(FPModBaseChain):
+class FPNormToPack(PipeModBaseChain):
 
     def __init__(self, pspec, e_extra=False):
         self.e_extra = e_extra
diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py
index 4553f531..4f906bd3 100644
--- a/src/ieee754/fpcommon/pack.py
+++ b/src/ieee754/fpcommon/pack.py
@@ -5,7 +5,7 @@
 from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBaseRecord, FPNumBase
 from ieee754.fpcommon.roundz import FPRoundData
 from ieee754.fpcommon.getop import FPPipeContext
@@ -38,7 +38,7 @@ class FPPackData:
         return list(self)
 
 
-class FPPackMod(FPModBase):
+class FPPackMod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "pack")
diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py
index 9f1720a2..d9e245b6 100644
--- a/src/ieee754/fpcommon/postnormalise.py
+++ b/src/ieee754/fpcommon/postnormalise.py
@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Cat, Mux
 from nmigen.cli import main, verilog
 from math import log
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import (Overflow, OverflowMod,
                                      FPNumBase, FPNumBaseRecord)
 from ieee754.fpcommon.fpbase import FPState
@@ -33,7 +33,7 @@ class FPNorm1Data:
         return ret
 
 
-class FPNorm1ModSingle(FPModBase):
+class FPNorm1ModSingle(PipeModBase):
 
     def __init__(self, pspec, e_extra=False):
         self.e_extra = e_extra
diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index 78a00d37..e061d2a1 100644
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -5,7 +5,7 @@
 from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
 from ieee754.fpcommon.getop import FPPipeContext
 from ieee754.fpcommon.postnormalise import FPNorm1Data
@@ -28,7 +28,7 @@ class FPRoundData:
         return ret
 
 
-class FPRoundMod(FPModBase):
+class FPRoundMod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "roundz")
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 9d92ea39..106da715 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -13,7 +13,7 @@ Relevant bugreports:
 from nmigen import Module, Signal, Cat, Elaboratable, Const, Mux
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.getop import FPPipeContext
@@ -21,7 +21,7 @@ from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation as DPCOp
 
 
-class FPDivStage0Mod(FPModBase):
+class FPDivStage0Mod(PipeModBase):
     """ DIV/SQRT/RSQRT "preparation" module.
 
         adjusts mantissa and exponent (sqrt/rsqrt exponent must be even),
diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index c1ffdee6..b62bec81 100644
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -12,12 +12,12 @@ Relevant bugreports:
 from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeOutputData
 
 
-class FPDivStage2Mod(FPModBase):
+class FPDivStage2Mod(PipeModBase):
     """ Last stage of div: preparation for normalisation.
 
         NOTE: this phase does NOT do ACTUAL DIV processing, it ONLY
diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index a147b068..e8829dcc 100644
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -4,7 +4,7 @@ Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 
 """
 
-from nmutil.pipemodbase import FPModBaseChain
+from nmutil.pipemodbase import PipeModBaseChain
 from ieee754.div_rem_sqrt_rsqrt.div_pipe import (DivPipeInterstageData,
                                                  DivPipeSetupStage,
                                                  DivPipeCalculateStage,
@@ -14,7 +14,7 @@ from ieee754.fpdiv.div0 import FPDivStage0Mod
 from ieee754.fpdiv.div2 import FPDivStage2Mod
 
 
-class FPDivStagesSetup(FPModBaseChain):
+class FPDivStagesSetup(PipeModBaseChain):
 
     def __init__(self, pspec, n_stages, stage_offs):
         self.n_stages = n_stages # number of combinatorial stages
@@ -48,7 +48,7 @@ class FPDivStagesSetup(FPModBaseChain):
         return divstages
 
 
-class FPDivStagesIntermediate(FPModBaseChain):
+class FPDivStagesIntermediate(PipeModBaseChain):
 
     def __init__(self, pspec, n_stages, stage_offs):
         self.n_stages = n_stages # number of combinatorial stages
@@ -75,7 +75,7 @@ class FPDivStagesIntermediate(FPModBaseChain):
         return divstages
 
 
-class FPDivStagesFinal(FPModBaseChain):
+class FPDivStagesFinal(PipeModBaseChain):
 
     def __init__(self, pspec, n_stages, stage_offs):
         self.n_stages = n_stages # number of combinatorial stages
diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py
index 5b637020..20f67028 100644
--- a/src/ieee754/fpdiv/specialcases.py
+++ b/src/ieee754/fpdiv/specialcases.py
@@ -13,7 +13,7 @@ from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 from math import log
 
-from nmutil.pipemodbase import FPModBase, FPModBaseChain
+from nmutil.pipemodbase import PipeModBase, PipeModBaseChain
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
@@ -21,7 +21,7 @@ from ieee754.fpmul.align import FPAlignModSingle
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation as DP
 
 
-class FPDIVSpecialCasesMod(FPModBase):
+class FPDIVSpecialCasesMod(PipeModBase):
     """ special cases: NaNs, infs, zeros, denormalised
         see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
@@ -150,7 +150,7 @@ class FPDIVSpecialCasesMod(FPModBase):
         return m
 
 
-class FPDIVSpecialCasesDeNorm(FPModBaseChain):
+class FPDIVSpecialCasesDeNorm(PipeModBaseChain):
     """ special cases: NaNs, infs, zeros, denormalised
     """
 
diff --git a/src/ieee754/fpmul/align.py b/src/ieee754/fpmul/align.py
index 507e21a4..b105f8ef 100644
--- a/src/ieee754/fpmul/align.py
+++ b/src/ieee754/fpmul/align.py
@@ -4,7 +4,7 @@ from nmigen import Module, Signal, Cat, Mux
 from nmigen.cli import main, verilog
 from math import log
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBase
 from ieee754.fpcommon.getop import FPPipeContext
 from ieee754.fpcommon.msbhigh import FPMSBHigh
@@ -12,7 +12,7 @@ from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 
 
-class FPAlignModSingle(FPModBase):
+class FPAlignModSingle(PipeModBase):
 
     def __init__(self, pspec, e_extra=False):
         self.e_extra = e_extra
diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index 398a953d..428c2753 100644
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -7,7 +7,7 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.getop import FPPipeContext
@@ -30,7 +30,7 @@ class FPMulStage0Data:
                 self.product.eq(i.product), self.ctx.eq(i.ctx)]
 
 
-class FPMulStage0Mod(FPModBase):
+class FPMulStage0Mod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "mul0")
diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index 9f896315..67e91517 100644
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -7,12 +7,12 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpmul.mul0 import FPMulStage0Data
 
 
-class FPMulStage1Mod(FPModBase):
+class FPMulStage1Mod(PipeModBase):
     """ Second stage of mul: preparation for normalisation.
     """
 
diff --git a/src/ieee754/fpmul/mulstages.py b/src/ieee754/fpmul/mulstages.py
index 78844cf8..95fc5be3 100644
--- a/src/ieee754/fpmul/mulstages.py
+++ b/src/ieee754/fpmul/mulstages.py
@@ -5,14 +5,14 @@ from nmigen.cli import main, verilog
 
 from nmutil.singlepipe import StageChain
 
-from nmutil.pipemodbase import FPModBaseChain
+from nmutil.pipemodbase import PipeModBaseChain
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpmul.mul0 import FPMulStage0Mod
 from ieee754.fpmul.mul1 import FPMulStage1Mod
 
 
-class FPMulStages(FPModBaseChain):
+class FPMulStages(PipeModBaseChain):
 
     def get_chain(self):
         # chain MulStage0 and MulStage1
diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index 97174430..fa834400 100644
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -6,13 +6,13 @@ from math import log
 
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
-from nmutil.pipemodbase import FPModBase, FPModBaseChain
+from nmutil.pipemodbase import PipeModBase, PipeModBaseChain
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
 from ieee754.fpmul.align import FPAlignModSingle
 
 
-class FPMulSpecialCasesMod(FPModBase):
+class FPMulSpecialCasesMod(PipeModBase):
     """ special cases: NaNs, infs, zeros, denormalised
         see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
@@ -87,7 +87,7 @@ class FPMulSpecialCasesMod(FPModBase):
         return m
 
 
-class FPMulSpecialCasesDeNorm(FPModBaseChain):
+class FPMulSpecialCasesDeNorm(PipeModBaseChain):
     """ special cases: NaNs, infs, zeros, denormalised
     """
 
diff --git a/src/nmutil/pipemodbase.py b/src/nmutil/pipemodbase.py
index 1ebe3a1a..0c5a02fa 100644
--- a/src/nmutil/pipemodbase.py
+++ b/src/nmutil/pipemodbase.py
@@ -3,8 +3,8 @@ from ieee754.pipeline import DynamicPipe
 from nmutil.singlepipe import StageChain
 
 
-class FPModBase(Elaboratable):
-    """FPModBase: common code between nearly every pipeline module
+class PipeModBase(Elaboratable):
+    """PipeModBase: common code between nearly every pipeline module
     """
     def __init__(self, pspec, modname):
         self.modname = modname # use this to give a name to this module
@@ -22,8 +22,8 @@ class FPModBase(Elaboratable):
         m.d.comb += self.i.eq(i)
 
 
-class FPModBaseChain(DynamicPipe):
-    """FPModBaseChain: common code between stage-chained pipes
+class PipeModBaseChain(DynamicPipe):
+    """PipeModBaseChain: common code between stage-chained pipes
 
     Links a set of combinatorial modules (get_chain) together
     and uses pspec.pipekls to dynamically select the pipeline type
-- 
2.30.2