From f310430d5ca4b48907db352bfe8fff7ac2b30929 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 10 Apr 2023 23:02:58 +0100 Subject: [PATCH] --- openpower/sv/normal.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 586c96e9e..4a136b93d 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -141,7 +141,7 @@ it is also possible to perform prefix-sum (Fibonacci Series) in certain circumstances. Details are in the [[svp64/appendix]] Reduce Mode should not be confused with Parallel Reduction [[sv/remap]]. -As explained in the [[sv/appendix]] Reduce Mode switches off the check +As explained in the [[sv/svp64/appendix]] Reduce Mode switches off the check which would normally stop looping if the result register is scalar. Thus, the result scalar register, if also used as a source scalar, may be used to perform sequential accumulation. This *deliberately* -- 2.30.2