From f4d33f9769f4d792f9243d174b8b1f42faf3a8e6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 31 Jan 2022 20:38:45 +0000 Subject: [PATCH] fix bug in itlb_valid SRLatch set/reset, a bit weird but it works --- src/soc/experiment/dcache.py | 4 ++-- src/soc/experiment/icache.py | 8 +++++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 4dc11e8a..936c60d7 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -83,9 +83,9 @@ from nmutil.util import wrap # TODO: make these parameters of DCache at some point LINE_SIZE = 64 # Line size in bytes NUM_LINES = 64 # Number of lines in a set -NUM_WAYS = 1 # Number of ways +NUM_WAYS = 2 # Number of ways TLB_SET_SIZE = 64 # L1 DTLB entries per set -TLB_NUM_WAYS = 1 # L1 DTLB number of sets +TLB_NUM_WAYS = 2 # L1 DTLB number of sets TLB_LG_PGSZ = 12 # L1 DTLB log_2(page_size) LOG_LENGTH = 0 # Non-zero to enable log data collection diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 2f0af7a2..f9d7f64c 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -443,14 +443,16 @@ class ICache(FetchUnitInterface, Elaboratable): comb += wr_unary.eq(1<