From f4f4d6f0d264891a1be2a3b8a3c267669663f6a3 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 30 Jun 2022 20:48:08 +0100
Subject: [PATCH]

---
 openpower/sv/mv.swizzle.mdwn | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 7273e4640..d82a18751 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -125,7 +125,9 @@ indivisible: an Exception or Interrupt may not occur during the Moves.
 
 Note that unlike the Vectorised variant, when `RT=RA` the Scalar variant
 *must* buffer (read) both 64-bit RA registers before writing to the
-RT pair. This ensures that register file corruption does not occur.
+RT pair (in an Out-of-Order Micro-architecture, both of the register
+pair must be "in-flight").
+This ensures that register file corruption does not occur.
 
 **SVP64 Vectorised**
 
-- 
2.30.2