From f515dc14fa487bc01de4b33ce6661163801d77c3 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 23 Nov 2018 00:01:27 +0000
Subject: [PATCH] add conversion code, see what happens

---
 cpu_fetch_stage.py | 62 ++++++++++++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 24 deletions(-)

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 242e2ef..469b21e 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -26,11 +26,11 @@
 from migen import *
 from migen.fhdl import verilog
 
-from riscvdefs import *
+#from riscvdefs import *
 from cpudefs import *
 
-reset_vector = 32'hXXXXXXXX;
-mtvec = 32'hXXXXXXXX;
+reset_vector = 0x0 #32'hXXXXXXXX;
+mtvec = 0x0 # 32'hXXXXXXXX;
 
 class CPUFetchStage(Module):
     def __init__(self):
@@ -48,31 +48,31 @@ class CPUFetchStage(Module):
         self.output_state = Signal(fetch_output_state,
                                    reset=fetch_output_state_empty)
 
-        self.comb += [
-            self.cd_sys.clk.eq(self.clk),
-            self.cd_sys.rst.eq(self.reset)
-        ]
+        #self.comb += [
+        #    self.cd_sys.clk.eq(self.clk),
+        #    self.cd_sys.rst.eq(self.reset)
+        #]
 
         fetch_pc = Signal(32, reset=reset_vector)
 
         self.sync += If(fetch_action != fetch_action_wait,
-                        output_pc.eq(fetch_pc))
+                        self.output_pc.eq(fetch_pc))
 
         memory_interface_fetch_address = fetch_pc[2:]
 
-        initial output_pc <= reset_vector;
-        initial output_state <= `fetch_output_state_empty;
+        #initial output_pc <= reset_vector;
+        #initial output_state <= `fetch_output_state_empty;
 
         delayed_instruction = Signal(32, reset=0)
         delayed_instruction_valid = Signal(reset=0)
 
-        self.sync += delayed_instruction.eq(output_instruction)
-        self.sync += output_state.eq(fetch_output_state_empty)
+        self.sync += delayed_instruction.eq(self.output_instruction)
+        self.sync += self.output_state.eq(fetch_output_state_empty)
 
         self.comb += If(delayed_instruction_valid,
-                    output_instruction.eq(delayed_instruction)
+                    self.output_instruction.eq(delayed_instruction)
                 ).Else(
-                    output_instruction.eq(memory_interface_fetch_data)
+                    self.output_instruction.eq(self.memory_interface_fetch_data)
                 )
 
         self.sync += delayed_instruction_valid.eq(fetch_action ==
@@ -80,31 +80,45 @@ class CPUFetchStage(Module):
 
         fc = {
             fetch_action_ack_trap:
-                If(memory_interface_fetch_valid,
+                If(self.memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
-                    output_state.eq(fetch_output_state_valid)]
+                    self.output_state.eq(fetch_output_state_valid)]
                 ).Else(
                    [fetch_pc.eq(mtvec),
-                    output_state.eq(fetch_output_state_trap)]
+                    self.output_state.eq(fetch_output_state_trap)]
                 ),
             fetch_action_fence:
-                [ fetch_pc.eq(output_pc + 4),
-                  output_state.eq(fetch_output_state_empty)
+                [ fetch_pc.eq(self.output_pc + 4),
+                  self.output_state.eq(fetch_output_state_empty)
                 ],
             fetch_action_jump:
-                [ fetch_pc.eq(target_pc),
-                  output_state.eq(fetch_output_state_empty)
+                [ fetch_pc.eq(self.target_pc),
+                  self.output_state.eq(fetch_output_state_empty)
                 ],
-            fetch_action_error_trap,
+            fetch_action_error_trap:
                    [fetch_pc.eq(mtvec),
-                    output_state.eq(fetch_output_state_empty)
+                    self.output_state.eq(fetch_output_state_empty)
                 ],
             fetch_action_wait:
                    [fetch_pc.eq(fetch_pc),
-                    output_state.eq(fetch_output_state_valid)
+                    self.output_state.eq(fetch_output_state_valid)
                 ]
         }
         fc[fetch_action_default] = fc[fetch_action_ack_trap]
         fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
         self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)
 
+if __name__ == "__main__":
+    example = CPUFetchStage()
+    memory_interface_fetch_address = Signal(32)
+    print(verilog.convert(example,
+         { #example.clk,
+           #example.reset,
+           memory_interface_fetch_address,
+           example.memory_interface_fetch_data,
+           example.memory_interface_fetch_valid,
+           example.fetch_action,
+           example.target_pc,
+           example.output_pc,
+           example.output_instruction,
+           example.output_state }))
-- 
2.30.2