From f55e8cde8a904d2e2017c2633dd94d9d98d2fae2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 Jan 2022 10:49:14 +0000 Subject: [PATCH] for second aligned request truncate address to nearest dword this ensures that DAR gets set correctly if a pagefault 0x300 occurs --- src/soc/fu/ldst/loadstore.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index 2b883d0d..500024aa 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -321,13 +321,16 @@ class LoadStore1(PortInterfaceBase): with m.If(ldst_r.load): m.d.comb += self.load_data[0:63].eq(d_in.data) sync += self.load_data_delay[0:64].eq(d_in.data) - # mmm kinda cheating, make a 2nd blip + # mmm kinda cheating, make a 2nd blip. + # use an aligned version of the address + addr_aligned, z3 = Signal(64), Const(0, 3) + comb += addr_aligned.eq(Cat(z3, ldst_r.raddr[3:]+1)) m.d.comb += self.d_validblip.eq(1) comb += self.req.eq(ldst_r) # from copy of request - comb += self.req.raddr.eq(ldst_r.raddr + 8) + comb += self.req.raddr.eq(addr_aligned) comb += self.req.byte_sel.eq(ldst_r.byte_sel[8:]) comb += self.req.alignstate.eq(Misalign.WAITSECOND) - sync += ldst_r.raddr.eq(ldst_r.raddr + 8) + sync += ldst_r.raddr.eq(addr_aligned) sync += ldst_r.byte_sel.eq(ldst_r.byte_sel[8:]) sync += ldst_r.alignstate.eq(Misalign.WAITSECOND) sync += Display(" second req %x", self.req.raddr) -- 2.30.2