From f5d15838b26bf15121af5e9e203d8cf2f673fdce Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 26 Mar 2023 19:23:27 +0100 Subject: [PATCH] ls008 only doing setvl and svstep --- openpower/sv/rfc/ls008.mdwn | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn index 3ae2a815b..02f1e9f0d 100644 --- a/openpower/sv/rfc/ls008.mdwn +++ b/openpower/sv/rfc/ls008.mdwn @@ -32,10 +32,6 @@ ``` setvl - Cray-style "Set Vector Length" instruction svstep - Vertical-First Mode explicit Step and Status - svremap - Re-Mapping of Register Element Offsets - svindex - General-purpose setting of SHAPEs to be re-mapped - svshape - Hardware-level setting of SHAPEs for element re-mapping - svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2) ``` **Submitter**: Luke Leighton (Libre-SOC) @@ -45,7 +41,7 @@ **Impact on processor**: ``` - Addition of six new "Zero-Overhead-Loop-Control" DSP-style Vector-style + Addition of two new "Zero-Overhead-Loop-Control" DSP-style Vector-style Management Instructions which can be implemented extremely efficiently and effectively by inserting an additional phase between Decode and Issue. More complex designs are NOT adversely impacted and in fact greatly benefit @@ -102,8 +98,8 @@ Add the following entries to: # Notation, Section 1.3.2 -When register operands (RA, RT, BF) are prefixed by a single underscore -(_RT, _RA, _BF) the variable contains the contents of the instruction field +When register operands (`RA, RT, BF`) are prefixed by a single underscore +(`_RT, _RA, _BF`) the variable contains the contents of the instruction field not the contents of the Register File referenced *by* that field. Example: `_RT` contains the contents of bits 5 thru 10. The relationship `RT = GPR(_RT)` is thus always true. Uses include making alternative -- 2.30.2