From f5ecf65e5e2c6e60355933b8a2aca230e8443ff5 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 9 Jun 2016 14:20:54 -0700 Subject: [PATCH] Trap on tdrdata registers when tdrselect[XLEN-1]=0 --- riscv/processor.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index ed9a83b..dac5d5b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -483,9 +483,6 @@ reg_t processor_t::get_csr(int which) case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; case CSR_TDRSELECT: return 0; - case CSR_TDRDATA1: return 0; - case CSR_TDRDATA2: return 0; - case CSR_TDRDATA3: return 0; case CSR_DCSR: { uint32_t v = 0; -- 2.30.2