From f76036eb280fc7a94674489e2a8ee975d030112e Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 3 Jul 2022 10:38:17 +0100 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index a3768bea9..2158d8dab 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -64,8 +64,7 @@ Page Faults etc. aside this is *guaranteed* 100% without fail to perform the contents into r0 through r63. Thus it becomes a "LOAD-MULTI". Twin Predication could even be used to only load relevant registers from the stack. This *only works if VL is set to the requested value* rather -than, as in RVV, allowing the hardware to set VL to an arbitrary value -(caveat being, limited to not exceed MVL) +than, as in RVV, allowing the hardware to set VL to an arbitrary value. Also available is the option to set VL from CTR (`VL = MIN(CTR, MVL)`. In combination with SVP64 [[sv/branches]] this can save one instruction @@ -116,7 +115,10 @@ Additional pseudo-op for obtaining VL without modifying it (or any state): For Vertical-First mode, a pseudo-op for explicit incrementing of srcstep and dststep: - svstep. : setvl. 0, 0, vf=1, vs=0, ms=0 + svfstep. : setvl. 0, 0, vf=1, vs=0, ms=0 + +This pseudocode op is different from [[sv/svstep]] which is used to +perform detailed enquiries about internal state. Note that whilst it is possible to set both MVL and VL from the same immediate, it is not possible to set them to different immediates in @@ -159,7 +161,7 @@ advance srcstep/dststep. An outer loop is expected to be used (branch instruction) which completes a series of Vector operations. -```svstep``` mode is enabled when vf=1, vs=0 and ms=0. +```svfstep``` mode is enabled when vf=1, vs=0 and ms=0. When Rc=1 it is possible to determine when any level of loops reach an end condition, or if VL has been reached. The immediate can be reinterpreted as indicating which SVSTATE (0-3) -- 2.30.2