From fa196a0945837ad32385471e405a381cde53ce4f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 22 Nov 2020 15:12:55 +0000 Subject: [PATCH] --- openpower/sv/toc_data_pointer.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/toc_data_pointer.mdwn b/openpower/sv/toc_data_pointer.mdwn index bca6430db..74b1c9d1f 100644 --- a/openpower/sv/toc_data_pointer.mdwn +++ b/openpower/sv/toc_data_pointer.mdwn @@ -30,9 +30,9 @@ What instead if this could be replaced by: where again, behind the scenes, a hidden micro-coded LD occurs at an address 8(TOC) to be loaded into the immediate operand, as if it were possible to have a full 64 bit operand in the cmpli instruction? -This could hypothetically be encoded with existing v3.0B instructions, loadingvthe 64 bit immediate into a temporary register, followed by using cmp rather than cmpi: +This could hypothetically be encoded with existing v3.0B instructions, loading the 64 bit immediate into a temporary register, followed by using cmp rather than cmpi: ld r9, 8(r10) # r10 loaded from TOC cmp r5, r9 -However the very fact that it requires the extra LD instruction (explicitly, rather than implicitly micro-coded) tells us that there is still a benefit to this approach. +However the very fact that it requires the extra LD instruction (explicitly, rather than implicitly micro-coded) tells us that there is still a benefit to this approach. Additionally: one less GPR is required. -- 2.30.2