From fc576b1ebe7809053214d5a8fc022cad5a1a7a14 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 Jan 2022 13:42:12 +0000 Subject: [PATCH] preserve bits of SRR1 on a TRAP (including all interrupts) which in turn means that PowerDecoder2 has to read SRR1 --- src/soc/fu/trap/main_stage.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 1685f3f2..2c8141de 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -65,6 +65,8 @@ class TrapMainStage(PipeModBase): op = self.i.ctx.op msr_i = op.msr svstate_i = op.svstate + + srr1_i = self.i.srr1 nia_o = self.o.nia svsrr0_o, srr0_o, srr1_o = self.o.svsrr0, self.o.srr0, self.o.srr1 @@ -76,7 +78,13 @@ class TrapMainStage(PipeModBase): comb += srr0_o.data.eq(return_addr) comb += srr0_o.ok.eq(1) - # take a copy of the current MSR into SRR1 + # take a copy of the current MSR into SRR1, but first copy old SRR1 + # this preserves the bits of SRR1 that are not supposed to change: + # MSR.IR,DR,PMM,RI,LE (0-5) and MR,FP,ME,FE0 (11-14) + # i would suggest reading v3.0C p1063 Book III section 7.2.1 for + # advice but it's so obscure and indirect, that it's just easier + # to copy microwatt behaviour. see writeback.vhdl + comb += srr1_o.data.eq(srr1_i) # preserve 0-5 and 11-14 comb += msr_copy(srr1_o.data, msr_i) # old MSR comb += srr1_o.ok.eq(1) -- 2.30.2