From ff3208652a668beaa776e2ab8a91d4e8c9d882e7 Mon Sep 17 00:00:00 2001
From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0"
 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Sun, 22 Nov 2020 20:21:59 +0000
Subject: [PATCH]

---
 HDL_workflow/ECP5_FPGA.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 11134812a..efb2b8523 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -55,6 +55,8 @@ Follow this section if you have the Versa ECP5 FPGA:
 
 Final steps for both FPGA boards:
 
+| Done?   | Checklist Step |
+|---------|----------------|
 |         | Check each jumper wire connection between the corresponding pins on the FPGA and the STLINKv2 **four** times |
 |         | I don't know what's next, need to review with lkcl |
 
-- 
2.30.2