From ea4b9f610cb8df52b7492062c61b18de79fb4a81 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Aug 2018 11:12:52 +0100 Subject: [PATCH] take out SDRAM memory-mapping addresses --- src/core/core_parameters.bsv | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/core/core_parameters.bsv b/src/core/core_parameters.bsv index d4afdb0..00d476b 100644 --- a/src/core/core_parameters.bsv +++ b/src/core/core_parameters.bsv @@ -405,8 +405,8 @@ `define BootRomEnd 'h00010FFF `define DMABase 'h00011600 `define DMAEnd 'h000116FF // TODO - `define SDRAMCfgBase 'h00011700 - `define SDRAMCfgEnd 'h000117FF // 12 32-bit registers + //`define SDRAMCfgBase 'h00011700 + //`define SDRAMCfgEnd 'h000117FF // 12 32-bit registers `define TCMBase 'h00020000 // `define TCMEnd 'h00040000 // 128KB `define VMEBase 'h40000000 @@ -418,13 +418,13 @@ `define FlexBusBase 'h50000000 `define FlexBusEnd 'h5FFFFFFF `endif - `ifdef FlexBus_verify - `define SDRAMMemBase 'h50000000 - `define SDRAMMemEnd 'h5FFFFFFF // 1GB - `else - `define SDRAMMemBase 'h80000000 - `define SDRAMMemEnd 'h8FFFFFFF // 1GB - `endif + //`ifdef FlexBus_verify + //`define SDRAMMemBase 'h50000000 + //`define SDRAMMemEnd 'h5FFFFFFF // 1GB + //`else + //`define SDRAMMemBase 'h80000000 + //`define SDRAMMemEnd 'h8FFFFFFF // 1GB + //`endif `define AxiExp1Base 'hC0000000 `define AxiExp1End 'hFFFFFFFF /*=================================================== */ -- 2.30.2