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Include abc change to fix FreeBSD build
2022-05-06 Miodrag MilanovicInclude abc change to fix FreeBSD build
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2022-05-02 Miodrag MilanovicAIM file could have gaps in or between inputs and inits
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2022-04-29 Miodrag MilanovićMerge pull request #3294 from YosysHQ/micko/verific_merge_pa...
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2022-04-29 Miodrag MilanovicIgnore merging past ffs that we are not properly merging
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2022-04-25 Miodrag MilanovićMerge pull request #3290 from mpasternacki/bugfix/freebsd...
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2022-04-25 Miodrag MilanovićMerge pull request #3289 from YosysHQ/micko/sim_improve
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2022-04-22 Miodrag MilanovicMatch $anyseq input if connected to public wire
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2022-04-22 Miodrag MilanovicTreat $anyseq as input from FST
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2022-04-22 Miodrag MilanovicIgnore change on last edge
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2022-04-22 Miodrag MilanovicLast sample from input does not represent change
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2022-04-22 Miodrag Milanoviclatches are always set to zero
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2022-04-22 Miodrag MilanovicIf not multiclock, output only on clock edges
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2022-04-22 Miodrag MilanovicSet init state for all wires from FST and set past
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2022-04-22 Miodrag MilanovicFix multiclock for btor2 witness
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2022-04-18 Miodrag MilanovićMerge pull request #3280 from YosysHQ/micko/fix_readaiw
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2022-04-18 Miodrag MilanovicUpdate abc
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2022-04-18 Miodrag Milanovicverific: allow memories to be inferred in loops (vhdl)
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2022-04-18 Miodrag MilanovićMerge pull request #3282 from nakengelhardt/verific_loop_rams
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2022-04-15 Miodrag MilanovicFix reading aiw from other solvers
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2022-04-08 Miodrag MilanovićMerge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
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2022-04-08 Miodrag MilanovicUse wrap_async_control_gate if ff is fine
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2022-04-08 Miodrag MilanovićMerge pull request #3273 from modwizcode/fix-build
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2022-04-05 Miodrag MilanovicReorder steps in -auto-top to fix synth command, fixes...
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2022-04-05 Miodrag MilanovicNext dev cycle
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2022-04-05 Miodrag MilanovicRelease version 0.16
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2022-04-04 Miodrag MilanovicUpdate CHANGELOG and manual
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2022-04-04 Miodrag MilanovićMerge pull request #3265 from YosysHQ/micko/sim_improvements
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2022-04-02 Miodrag Milanovicpast_ad initial value setting
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2022-04-02 Miodrag MilanovicsetInitState can be only one altering values
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2022-04-02 Miodrag MilanovicSet past_d value for init state
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2022-04-01 Miodrag MilanovićMerge pull request #3263 from YosysHQ/micko/clk2ff_init
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2022-04-01 Miodrag MilanovicSet init values for wrapped async control signals
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2022-04-01 Miodrag MilanovićMerge pull request #3262 from YosysHQ/micko/verific_hiernet
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2022-04-01 Miodrag MilanovicPreserve internal wires for external nets
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2022-03-31 Miodrag MilanovićMerge pull request #3256 from YosysHQ/micko/aiw_multiclock
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2022-03-31 Miodrag Milanovic Support memories in aiw and multiclock
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2022-03-30 Miodrag MilanovićMerge pull request #3259 from YosysHQ/micko/verific_valgrind
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2022-03-30 Miodrag MilanovicFix valgrind tests when using verific
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2022-03-30 Miodrag MilanovićMerge pull request #3260 from YosysHQ/micko/proper_scopename
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2022-03-30 Miodrag MilanovicProper scope naming from FST
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2022-03-30 Miodrag MilanovićMerge pull request #3250 from YosysHQ/micko/verific_consistent
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2022-03-29 Miodrag MilanovićMerge pull request #3258 from jix/fix-no-assertions
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2022-03-28 Miodrag MilanovićUpdate URL to zlib
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2022-03-26 Miodrag MilanovicProperly mark modules imported
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2022-03-25 Miodrag MilanovićMerge pull request #3249 from YosysHQ/micko/no_startoffset
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2022-03-25 Miodrag MilanovicImport verific netlist in consistent order
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2022-03-25 Miodrag MilanovicAdd -no-startoffset option to write_aiger
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2022-03-24 Miodrag MilanovićMerge pull request #3243 from nakengelhardt/fix_aiw_comment
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2022-03-22 Miodrag MilanovicUpdate abc with latest fix
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2022-03-22 Miodrag MilanovicProper SigBit forming in sim
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2022-03-22 Miodrag MilanovicProper SigBit forming in sim
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2022-03-18 Miodrag MilanovicMore verbose warnings
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2022-03-17 Miodrag MilanovićMerge pull request #3236 from YosysHQ/micko/tb_initial
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2022-03-16 Miodrag MilanovicRecognize registers and set initial state for them...
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2022-03-16 Miodrag MilanovicUpdate sim help message.
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2022-03-14 Miodrag MilanovićMerge pull request #3232 from YosysHQ/micko/fst2tb
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2022-03-14 Miodrag MilanovicAdded fst2tb pass for generating testbench
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2022-03-14 Miodrag MilanovicProper example code
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2022-03-11 Miodrag MilanovićMerge pull request #3229 from YosysHQ/micko/sim_date
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2022-03-11 Miodrag MilanovićMerge pull request #3222 from zachjs/prune-linux-ci
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2022-03-11 Miodrag MilanovićMerge pull request #3228 from YosysHQ/micko/disable_tests
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2022-03-11 Miodrag MilanovicAdd date parameter to enable full date/time and version...
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2022-03-11 Miodrag MilanovićMerge pull request #3226 from YosysHQ/micko/btor2witness
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2022-03-11 Miodrag MilanovicFstData already do conversion to VCD
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2022-03-11 Miodrag MilanovicSupport cell name in btor witness file
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2022-03-11 Miodrag Milanovichandle state names of $anyconst and $anyseq
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2022-03-11 Miodrag MilanovicProper write of memory data
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2022-03-10 Miodrag MilanovicDisable tests on most of platforms
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2022-03-09 Miodrag MilanovicStart work on memory init
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2022-03-09 Miodrag MilanovicFixes and error check
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2022-03-07 Miodrag Milanoviccleanup
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2022-03-07 Miodrag MilanovicError checks for aiger witness
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2022-03-07 Miodrag Milanovicbtor2 witness co-simulation
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2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
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2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_print_id
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2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
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2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape_quotes
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2022-03-04 Miodrag MilanovicNext dev cycle
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2022-03-04 Miodrag MilanovicRelease version 0.15
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2022-03-04 Miodrag MilanovicUpdate ABC
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2022-03-04 Miodrag MilanovicUpdate documentation
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2022-03-04 Miodrag MilanovićMerge pull request #3219 from YosysHQ/micko/quick_vcd
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2022-03-04 Miodrag MilanovićMerge pull request #3220 from YosysHQ/claire/simstuff
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2022-03-02 Miodrag MilanovicAdd option to ignore X only signals in output
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2022-03-02 Miodrag MilanovicWrite simulation files after simulation is performed
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2022-03-02 Miodrag MilanovicUpdate CHANGELOG
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2022-03-02 Miodrag MilanovicCleanup
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2022-02-28 Miodrag MilanovicRefactor sim output writers
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2022-02-28 Miodrag MilanovicQuick fix
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2022-02-28 Miodrag MilanovicVCD reader support by using external tool
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2022-02-28 Miodrag MilanovićMerge pull request #3216 from YosysHQ/claire/simstuff
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2022-02-27 Miodrag MilanovicSupport extended aiw format
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2022-02-25 Miodrag MilanovicFix for last clock edge data
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2022-02-21 Miodrag MilanovićMerge pull request #3203 from YosysHQ/micko/sim_ff
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2022-02-21 Miodrag MilanovicFix handling of ce_over_srst
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2022-02-18 Miodrag MilanovicChanged error message
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2022-02-18 Miodrag MilanovicAdded AIGER witness file co simulation
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2022-02-18 Miodrag Milanovicsimplify logic of handling flip-flops and latches
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2022-02-17 Miodrag MilanovicReview cleanup
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2022-02-16 Miodrag MilanovicRemove quotes if any from attribute
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