git.libre-soc.org Git - gram.git/search

2022-02-25	Luke Kenneth Casson...	allow DDR3 reset (rst) signal to be controlled by DFI...	commit \| commitdiff \| tree
2022-02-24	Luke Kenneth Casson...	add a BitSlip module	commit \| commitdiff \| tree
2022-02-24	Luke Kenneth Casson...	replace the simulation Clock-Reset-Generator with one...	commit \| commitdiff \| tree
2022-02-24	Luke Kenneth Casson...	add CSRs to FakePHY which allows at least testing of...	commit \| commitdiff \| tree
2022-02-22	Luke Kenneth Casson...	remove continue/skip and add comment that all	commit \| commitdiff \| tree
2022-02-21	Luke Kenneth Casson...	add debug print statements to investigate FakePHY	commit \| commitdiff \| tree
2022-02-21	Luke Kenneth Casson...	add a debug verilog dump of one of the FakePHY SocTest...	commit \| commitdiff \| tree
2022-02-20	Luke Kenneth Casson...	add dfii submodules so they get explicit names	commit \| commitdiff \| tree
2022-02-20	Luke Kenneth Casson...	add name to DFI Interface (helps gtkwave traces)	commit \| commitdiff \| tree
2022-02-19	Luke Kenneth Casson...	fix gram unit test imports	commit \| commitdiff \| tree
2022-02-16	Luke Kenneth Casson...	fix ECP5DDRPHY cs declaration	commit \| commitdiff \| tree