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2021-06-09	Jean-Paul Chaput	I/O pads reorganisation, 32 per side (except for NORTH).	commit \| commitdiff \| tree
2021-06-09	Jean-Paul Chaput	P&R tweaks for routing convergence.	commit \| commitdiff \| tree
2021-06-09	Jean-Paul Chaput	Add a case in the build script to fit my environment...	commit \| commitdiff \| tree
2021-06-09	Jean-Paul Chaput	Remove files that are now copied from other locations.	commit \| commitdiff \| tree
2021-06-08	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-06-08	Jean-Paul Chaput	Adpapt e9/TSMC doDesign to the new size of the SRAMs...	commit \| commitdiff \| tree
2021-06-04	Jean-Paul Chaput	Updated experiments12 for the latest Coriolis.	commit \| commitdiff \| tree
2021-06-04	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-06-04	Jean-Paul Chaput	Updated configuration suited for experiment9/tsmc_c018.	commit \| commitdiff \| tree
2021-04-28	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-04-28	Jean-Paul Chaput	Management of SRAMs block at Coriolis devel.	commit \| commitdiff \| tree
2021-04-25	Jean-Paul Chaput	Correct setup for experiment9/freepdk_c4m45, restrict...	commit \| commitdiff \| tree
2021-04-24	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-04-24	Jean-Paul Chaput	Forgot to update experiments9 doDesign file for FreePDK 45.	commit \| commitdiff \| tree
2021-04-24	Jean-Paul Chaput	Keep in synch with the latest Coriolis. SRAM models...	commit \| commitdiff \| tree
2021-04-24	Jean-Paul Chaput	Correct settings for experiment10_verilog & FreePDK45.	commit \| commitdiff \| tree
2021-03-29	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-03-29	Jean-Paul Chaput	Add a placeholder for the PLL in the doDesign.py for...	commit \| commitdiff \| tree
2021-03-23	Jean-Paul Chaput	Uodated doDesign for the latest ls180 (sram variant).	commit \| commitdiff \| tree
2021-03-16	Jean-Paul Chaput	Add experiment9/symbolic to test the multiple drivers...	commit \| commitdiff \| tree
2021-03-14	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-03-14	Jean-Paul Chaput	Adjusted doDesign.py scripts to use Chip.doChipFloorplan().	commit \| commitdiff \| tree
2021-03-09	Jean-Paul Chaput	Forgot the Makefile, stupid!	commit \| commitdiff \| tree
2021-03-09	Jean-Paul Chaput	First working version of the Flexlib + P&R flow for...	commit \| commitdiff \| tree
2021-03-05	Jean-Paul Chaput	Added support files for ls180+SRAM on TSMC 180nm.	commit \| commitdiff \| tree
2021-03-02	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-03-02	Jean-Paul Chaput	First working power plane in experiment12.	commit \| commitdiff \| tree
2021-02-17	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-02-17	Jean-Paul Chaput	First working integration of a SRAM block.	commit \| commitdiff \| tree
2021-02-01	Jean-Paul Chaput	Netlist integration of the SRAM OK. Layout in progress.	commit \| commitdiff \| tree
2021-01-28	Jean-Paul Chaput	Working bench design with SRAM in top block.	commit \| commitdiff \| tree
2021-01-27	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-01-27	Jean-Paul Chaput	Pinmux loading is now integrated in Coriolis.	commit \| commitdiff \| tree
2020-11-30	Jean-Paul Chaput	Added experiments11, base for full chip with FlexLib...	commit \| commitdiff \| tree
2020-11-02	Jean-Paul Chaput	Completed experiment10, adder with JTAG (dual clocks...	commit \| commitdiff \| tree
2020-10-25	Jean-Paul Chaput	Added one-clock generated add.vst.	commit \| commitdiff \| tree
2020-10-25	Jean-Paul Chaput	Experiment10 switched to the new chip2core module.	commit \| commitdiff \| tree
2020-09-30	Jean-Paul Chaput	URL of submodule pinmux needs to use ssh/port 922.	commit \| commitdiff \| tree
2020-09-15	Jean-Paul Chaput	Use Yosys flattening for top blocks.	commit \| commitdiff \| tree
2020-09-14	Jean-Paul Chaput	Configuration updated for test of HFNS.	commit \| commitdiff \| tree
2020-08-12	Jean-Paul Chaput	Added doDesignFlat.py to P&R issuer in a flat way.	commit \| commitdiff \| tree
2020-08-11	Jean-Paul Chaput	Correct taking in accounts of the parameters settings.	commit \| commitdiff \| tree
2020-08-07	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2020-08-07	Jean-Paul Chaput	Use of CfgCache. Little beautificaton of doDesign.py	commit \| commitdiff \| tree
2020-08-03	Jean-Paul Chaput	Fisrt attempt at floorplaning test_issuer.	commit \| commitdiff \| tree
2020-06-30	Jean-Paul Chaput	Added experments9, a first taste at the full scale...	commit \| commitdiff \| tree
2020-06-06	Jean-Paul Chaput	Test of the FU-FU matrix 30x30 with Coriolis matrixplacer.	commit \| commitdiff \| tree
2020-04-20	Jean-Paul Chaput	Forgot to witre about block rotation.	commit \| commitdiff \| tree
2020-04-20	Jean-Paul Chaput	Optimized (datapath) placement and direct place.	commit \| commitdiff \| tree
2020-03-04	Jean-Paul Chaput	Correct configuration for fpmul64.	commit \| commitdiff \| tree

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