yosys.git
2022-03-31 Miodrag MilanovićMerge pull request #3256 from YosysHQ/micko/aiw_multiclock
2022-03-31 Miodrag Milanovic Support memories in aiw and multiclock
2022-03-31 github-actions... Bump version
2022-03-30 Miodrag MilanovićMerge pull request #3259 from YosysHQ/micko/verific_val...
2022-03-30 Miodrag MilanovicFix valgrind tests when using verific
2022-03-30 Miodrag MilanovićMerge pull request #3260 from YosysHQ/micko/proper_scop...
2022-03-30 Miodrag MilanovicProper scope naming from FST
2022-03-30 Miodrag MilanovićMerge pull request #3250 from YosysHQ/micko/verific_con...
2022-03-30 github-actions... Bump version
2022-03-29 Miodrag MilanovićMerge pull request #3258 from jix/fix-no-assertions
2022-03-29 Jannis Hardersmtbmc: fix bmc with no assertions
2022-03-29 github-actions... Bump version
2022-03-28 Marcelina Kościelnickakernel/mem: Only use FF init in read-first emu for...
2022-03-28 Jannis HarderMerge pull request #3253 from jix/smtbmc-nodeepcopy
2022-03-28 Jannis HarderMerge pull request #3247 from jix/smtbmc-keepgoing
2022-03-28 LoftyMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-03-28 LoftyMerge pull request #3246 from YosysHQ/gatecat/timing...
2022-03-28 Tim Pamborgowin: Add oscillator primitives
2022-03-28 Jannis Hardersmtbmc: Avoid unnecessary deep copies during unrolling
2022-03-28 Miodrag MilanovićUpdate URL to zlib
2022-03-26 Miodrag MilanovicProperly mark modules imported
2022-03-26 github-actions... Bump version
2022-03-25 NotAFileAdd some more reserve calls to RTLIL::Const
2022-03-25 Miodrag MilanovićMerge pull request #3249 from YosysHQ/micko/no_startoffset
2022-03-25 Miodrag MilanovicImport verific netlist in consistent order
2022-03-25 Miodrag MilanovicAdd -no-startoffset option to write_aiger
2022-03-25 github-actions... Bump version
2022-03-24 Miodrag MilanovićMerge pull request #3243 from nakengelhardt/fix_aiw_comment
2022-03-24 Jannis Harderyosys-smtbmc: Option to keep going after failed asserti...
2022-03-24 Jannis Harderyosys-smtbmc: Fix typo in help text, remove trailing...
2022-03-24 gatecatabc9_ops: Also derive blackboxes with timing info
2022-03-24 N. Engelhardtignore # comment lines
2022-03-23 github-actions... Bump version
2022-03-22 Miodrag MilanovicUpdate abc with latest fix
2022-03-22 Miodrag MilanovicProper SigBit forming in sim
2022-03-22 Miodrag MilanovicProper SigBit forming in sim
2022-03-22 github-actions... Bump version
2022-03-21 Marcelina Kościelnickaxilinx: Add RAMB4* blackboxes
2022-03-19 github-actions... Bump version
2022-03-18 Miodrag MilanovicMore verbose warnings
2022-03-17 Miodrag MilanovićMerge pull request #3236 from YosysHQ/micko/tb_initial
2022-03-17 github-actions... Bump version
2022-03-16 Miodrag MilanovicRecognize registers and set initial state for them...
2022-03-16 Miodrag MilanovicUpdate sim help message.
2022-03-15 github-actions... Bump version
2022-03-14 YRabbitgowin: add support for Double Data Rate primitives
2022-03-14 Miodrag MilanovićMerge pull request #3232 from YosysHQ/micko/fst2tb
2022-03-14 Miodrag MilanovicAdded fst2tb pass for generating testbench
2022-03-14 Claire XenMerge pull request #3213 from antonblanchard/abc-typo
2022-03-14 Miodrag MilanovicProper example code
2022-03-12 github-actions... Bump version
2022-03-11 Miodrag MilanovićMerge pull request #3229 from YosysHQ/micko/sim_date
2022-03-11 Miodrag MilanovićMerge pull request #3222 from zachjs/prune-linux-ci
2022-03-11 Miodrag MilanovićMerge pull request #3228 from YosysHQ/micko/disable_tests
2022-03-11 Claire Xenia... Add "sim -q" option
2022-03-11 Miodrag MilanovicAdd date parameter to enable full date/time and version...
2022-03-11 Claire Xenia... Small fix in "sim" help message
2022-03-11 Miodrag MilanovićMerge pull request #3226 from YosysHQ/micko/btor2witness
2022-03-11 Miodrag MilanovicFstData already do conversion to VCD
2022-03-11 Miodrag MilanovicSupport cell name in btor witness file
2022-03-11 Claire Xenia... Fix handling of some formal cells in btor back-end
2022-03-11 Miodrag Milanovichandle state names of $anyconst and $anyseq
2022-03-11 Zachary SnowPrune Linux CI builds
2022-03-11 Miodrag MilanovicProper write of memory data
2022-03-10 Miodrag MilanovicDisable tests on most of platforms
2022-03-10 github-actions... Bump version
2022-03-09 Loftyintel_alm: M10K write-enable is negative-true
2022-03-09 Miodrag MilanovicStart work on memory init
2022-03-09 Miodrag MilanovicFixes and error check
2022-03-07 Miodrag Milanoviccleanup
2022-03-07 Miodrag MilanovicError checks for aiger witness
2022-03-07 Miodrag Milanovicbtor2 witness co-simulation
2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
2022-03-05 github-actions... Bump version
2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_...
2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape...
2022-03-04 Miodrag MilanovicNext dev cycle
2022-03-04 Miodrag MilanovicRelease version 0.15 yosys-0.15
2022-03-04 Miodrag MilanovicUpdate ABC
2022-03-04 Miodrag MilanovicUpdate documentation
2022-03-04 Miodrag MilanovićMerge pull request #3219 from YosysHQ/micko/quick_vcd
2022-03-04 Miodrag MilanovićMerge pull request #3220 from YosysHQ/claire/simstuff
2022-03-03 github-actions... Bump version
2022-03-02 Miodrag MilanovicAdd option to ignore X only signals in output
2022-03-02 Miodrag MilanovicWrite simulation files after simulation is performed
2022-03-02 Miodrag MilanovicUpdate CHANGELOG
2022-03-02 Claire XenMerge pull request #3224 from YosysHQ/micko/refactor
2022-03-02 Miodrag MilanovicCleanup
2022-03-01 github-actions... Bump version
2022-02-28 Miodrag MilanovicRefactor sim output writers
2022-02-28 Miodrag MilanovicQuick fix
2022-02-28 Claire Xenia... Add writing of aiw files to "sim" command
2022-02-28 Claire Xenia... Hotfix in AIGER witness reader state machine
2022-02-28 Miodrag MilanovicVCD reader support by using external tool
2022-02-28 Miodrag MilanovićMerge pull request #3216 from YosysHQ/claire/simstuff
2022-02-27 Miodrag MilanovicSupport extended aiw format
2022-02-25 Miodrag MilanovicFix for last clock edge data
2022-02-25 Claire Xenia... Experimental sim changes
2022-02-25 github-actions... Bump version
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