experiment with nmigen verilog generation
[soclayout.git] / experiments10_verilog /
drwxr-xr-x   ..
-rwxr-xr-x 932 Makefile
-rw-r--r-- 1665 add.py
drwxr-xr-x - coriolis2
-rw-r--r-- 4005 doDesign.py
lrwxrwxrwx 11 mksym.sh -> ../mksym.sh
-rw-r--r-- 29 netlists.txt