Add an alternative partitioned equals combiner module
[ieee754fpu.git] / src / ieee754 / part_cmp /
drwxr-xr-x   ..
-rw-r--r-- 4720 equal.py
drwxr-xr-x - formal
-rw-r--r-- 4392 ge.py
-rw-r--r-- 1744 partition_combiner.py