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add SVSRR0 to FastRegsEnum
[soc.git] / src / soc / regfile /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py blob | history | raw
drwxr-xr-x - formal tree | history
-rw-r--r-- 13403 regfile.py blob | history | raw
-rw-r--r-- 7859 regfiles.py blob | history | raw
-rw-r--r-- 1144 util.py blob | history | raw
-rw-r--r-- 6279 virtual_port.py blob | history | raw