From 3fb49d5502f0cea65463a58669e803f642ce9c90 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 28 May 2019 05:54:31 +0100 Subject: [PATCH] reword multiplier section --- updates/018_2019may27_nlnet_grant_approved.mdwn | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/updates/018_2019may27_nlnet_grant_approved.mdwn b/updates/018_2019may27_nlnet_grant_approved.mdwn index f6451f6..fcf3e56 100644 --- a/updates/018_2019may27_nlnet_grant_approved.mdwn +++ b/updates/018_2019may27_nlnet_grant_approved.mdwn @@ -75,10 +75,8 @@ Adder and Multiplier Unit. Given that we are doing a Vector Processing front-end onto SIMD back-end operations, it makes sense to save gates by allowing the ADD and MUL units to be able to optionally handle a batch of 8-bit operations, or half the number of 16-bit operations, or a quarter -of the number of 32-bit operations or just one 64-bit operation. Or, -it can be used to do two 64-bit multiplications per cycle, or generate -4 32-bit results, or 8 16-bit results and so on, requiring a lot less gates -than if they were separate units. +of the number of 32-bit operations or just one 64-bit operation. +In this way, a lot less gates are required than if they were separate units. The unit tests demonstrate that the code that Jacob has written provide RISC-V mul, mulh, mulhu and mulhsu functionality. -- 2.30.2