From 665ad9014a6abdaa716c446b2b20b22a65d52477 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 28 May 2019 09:45:15 +0100 Subject: [PATCH] spelling corrections --- updates/018_2019may27_nlnet_grant_approved.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/updates/018_2019may27_nlnet_grant_approved.mdwn b/updates/018_2019may27_nlnet_grant_approved.mdwn index 9e35bbd..6c07056 100644 --- a/updates/018_2019may27_nlnet_grant_approved.mdwn +++ b/updates/018_2019may27_nlnet_grant_approved.mdwn @@ -75,7 +75,7 @@ Adder and Multiplier Unit. Given that we are doing a Vector Processing front-end onto SIMD back-end operations, it makes sense to save gates by allowing the ADD and MUL units to be able to optionally handle a batch of 8-bit operations, or half the number of 16-bit operations, or a quarter -of the number of 32-bit operations or one eigth of the number of64-bit +of the number of 32-bit operations or one eighth of the number of 64-bit operations. In this way, a lot less gates are required than if they were separate units. The unit tests demonstrate that the code that Jacob has written provide RISC-V mul, mulh, mulhu and mulhsu functionality. -- 2.30.2