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jtag: Sample data input on negative clock edge
authorGreg Davill <greg.davill@gmail.com>
Sat, 31 Oct 2020 12:19:19 +0000 (22:49 +1030)
committerGreg Davill <greg.davill@gmail.com>
Sat, 31 Oct 2020 12:19:19 +0000 (22:49 +1030)
commitb4d5e0e9ee1a3c13c00877e5895be441bd2c618f
tree8539459ffed84e08ec023c32d0b8cc278f4da501tree
parent1bbae8d1fdcdf87163c85faeb523ba6b30fb1257commit | diff
jtag: Sample data input on negative clock edge

Verification is off by 1bit when sampling on the rising edge.
Sampling on the megative edge also seems like a better option in
general.
ecpprog/jtag_tap.c diff | blob | history