common.mk

   1 # See LICENSE for license details.
   2
   3 # Required variables:
   4 # - MODEL
   5 # - PROJECT
   6 # - CONFIG_PROJECT
   7 # - CONFIG
   8 # - BUILD_DIR
   9 # - FPGA_DIR
  10
  11 # Optional variables:
  12 # - EXTRA_FPGA_VSRCS
  13
  14 # export to bootloader
  15 export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
  16
  17 # export to fpga-shells
  18 export FPGA_TOP_SYSTEM=$(MODEL)
  19 export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
  20 export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
  21 export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
  22
  23 export BUILD_DIR
  24
  25 EXTRA_FPGA_VSRCS ?=
  26 PATCHVERILOG ?= ""
  27 BOOTROM_DIR ?= ""
  28
  29 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
  30 export rocketchip_dir := $(base_dir)/rocket-chip
  31 SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
  32
  33 # Build firrtl.jar and put it where chisel3 can find it.
  34 FIRRTL_JAR ?= $(rocketchip_dir)/firrtl/utils/bin/firrtl.jar
  35 FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
  36
  37 $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
  38         $(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
  39         touch $(FIRRTL_JAR)
  40         mkdir -p $(rocketchip_dir)/lib
  41         cp -p $(FIRRTL_JAR) rocket-chip/lib
  42         mkdir -p $(rocketchip_dir)/chisel3/lib
  43         cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
  44
  45 # Build .fir
  46 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
  47 $(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
  48         mkdir -p $(dir $@)
  49         $(SBT) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
  50
  51 .PHONY: firrtl
  52 firrtl: $(firrtl)
  53
  54 # Build .v
  55 verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
  56 $(verilog): $(firrtl) $(FIRRTL_JAR)
  57         $(FIRRTL) -i $(firrtl) -o $@ -X verilog
  58 ifneq ($(PATCHVERILOG),"")
  59         $(PATCHVERILOG)
  60 endif
  61
  62 .PHONY: verilog
  63 verilog: $(verilog)
  64
  65 romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
  66 $(romgen): $(verilog)
  67 ifneq ($(BOOTROM_DIR),"")
  68         $(MAKE) -C $(BOOTROM_DIR) romgen
  69         mv $(BUILD_DIR)/rom.v $@
  70 endif
  71
  72 .PHONY: romgen
  73 romgen: $(romgen)
  74
  75 f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
  76 $(f):
  77         echo $(VSRCS) > $@
  78
  79 bit := $(BUILD_DIR)/obj/$(MODEL).bit
  80 $(bit): $(romgen) $(f)
  81         cd $(BUILD_DIR); vivado \
  82                 -nojournal -mode batch \
  83                 -source $(fpga_common_script_dir)/vivado.tcl \
  84                 -tclargs \
  85                 -top-module "$(MODEL)" \
  86                 -F "$(f)" \
  87                 -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
  88                 -board "$(BOARD)"
  89
  90
  91 # Build .mcs
  92 mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
  93 $(mcs): $(bit)
  94         cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
  95
  96 .PHONY: mcs
  97 mcs: $(mcs)
  98
  99 # Clean
 100 .PHONY: clean
 101 clean:
 102 ifneq ($(BOOTROM_DIR),"")
 103         $(MAKE) -C $(BOOTROM_DIR) clean
 104 endif
 105         $(MAKE) -C $(FPGA_DIR) clean
 106         rm -rf $(BUILD_DIR)