Merge pull request #44 from sifive/bump-sifive-blocks

[freedom-sifive.git] / README.md

diff --git a/README.md b/README.md
index 940b3d0b02907e3a3db6d6889e7b9f889501cd0f..f1d22ac0ea74e5aa5c748fa1e594846fe66ac65c 100644 (file)
--- a/README.md
+++ b/README.md
@@ -44,6 +44,8 @@ $ make -f Makefile.e300artydevkit verilog
 $ make -f Makefile.e300artydevkit mcs
 ```
 
+Note: This flow requires vivado 2017.1. Old versions are known to fail.
+
 These will place the files under `builds/e300artydevkit/obj`.
 
 Note that in order to run the `mcs` target, you need to have the `vivado`
@@ -55,6 +57,9 @@ The default bootrom consists of a program that immediately jumps to address
 0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
 board.
 
+### Using the generated MCS Image
+
+For instructions for getting the generated image onto an FPGA and programming it with software using the [Freedom E SDK](https://github.com/sifive/freedom-e-sdk), please see the [Freedom E310 Arty FPGA Dev Kit Getting Started Guide](https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/).
 
 Freedom U500 VC707 FPGA Dev Kit
 -------------------------------
@@ -77,6 +82,8 @@ $ make -f Makefile.u500vc707devkit verilog
 $ make -f Makefile.u500vc707devkit mcs
 ```
 
+Note: This flow requires vivado 2016.1. Newer versions are known to fail.
+
 These will place the files under `builds/u500vc707devkit/obj`.
 
 Note that in order to run the `mcs` target, you need to have the `vivado`