From 7b4588e1710b0e997b9dd5d1f0376150afe276ce Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Aug 2019 11:17:55 +0100 Subject: [PATCH] remove need to pass register_levels to AddReduceSingle --- src/ieee754/part_mul_add/multiply.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py index 672bbfd3..92afc2bb 100644 --- a/src/ieee754/part_mul_add/multiply.py +++ b/src/ieee754/part_mul_add/multiply.py @@ -616,7 +616,7 @@ class AddReduce(Elaboratable): m.d.comb += i.eq_from(partition_points, inputs, part_ops) for idx in range(len(self.levels)): mcur = self.levels[idx] - if 0 in mcur.register_levels: + if idx in self.register_levels: m.d.sync += mcur.i.eq(i) else: m.d.comb += mcur.i.eq(i) -- 2.30.2