harmonised_rvv_rvp.mdwn

   1 # Proposal to harmonise RV Vector spec with Andes Packed SIMD ("Harmonised" RVP)
   2
   3 [[Comparative analysis|harmonised_rvv_rvp/comparative_analysis]] of
   4 Harmonised RVP vs Andes Packed SIMD ISA proposal
   5
   6 **MVL, setvl instruction & VL CSR work as per RV Vector spec.**
   7
   8 **VLD and VST are supported**
   9
  10 RVP implementations may choose to load/store to/from Integer register file
  11 (rather than from a dedicated Vector register file).
  12
  13 * Thus, RVP implementations have a choice of providing a dedicated
  14   Vector register file, or sharing the integer register file, but not
  15   both  simultaneously.  (Supporting both would need a CSR mode switch bit).
  16 * Mapping of v0-31 <-> r0-31 **is fixed** at 1:1.  (An exception may be
  17   made to map v1 to r5, as otherwise may clash with procedure linkage).
  18 * VLD and VST in this case will have similar behaviour to LW/LD and SW/SD
  19   respectively, but only operate on up to VL elements (see point #4 below).
  20 * If integer register file is used for vector operations, any callee saved
  21   registers (r2-4, 8-9, 18-27) must be saved with RVI SW or SD instructions,
  22   before being used as vector registers (this register saving behaviour is
  23   harmless but redundant when RVP code is run on a machine with a dedicated
  24   vector reg file).
  25
  26 **VLDX, VSTX, VLDS, VSTS are not supported in hardware**
  27 To keep RVP implementations simple, these instructions will trap, and
  28 may be implemented as software emulation
  29
  30 **Default register "banks" and types**
  31
  32 In the absence of an explicit VCFG setup, the vector registers (when
  33 shared with Integer register file) are to default into two “banks”
  34 as follows:
  35
  36 * v0-v15:    vectors with INT8 elements, split into signed (v0-v7)
  37   & unsigned (v8-v15)
  38 * v16-v29:  vectors with INT16 elements, split into signed (v16-v23)
  39   & unsigned (v24-v29)
  40
  41 Having the above default vector type configuration harmonises most of
  42 the Andes SIMD instruction set (which explicitly encodes INT8 vs INT16
  43 vector types as separate instructions).  The main change from the Andes
  44 SIMD proposal is that instructions are restricted to 14 registers of
  45 each vector element type (with element size explicitly encoded in the
  46 most significant bit of the 5 bit register specifier fields).
  47
  48 Notes:
  49
  50 * To preserve forward RVV compatibility, programmers should still
  51   explicitly setup VDCFG to the above default vector types
  52 * Essentially the same register allocation algorithm used for RVV can be
  53   used for RVP, except the algorithm should preferentially use temporary
  54   registers first, before using saved registers
  55 * v30-v31 are reserved for 32 bit operations (see Section 2.3 of this
  56   document), and hence not part of the register bank of INT16 vectors.
  57 * v0 is mapped to r1 (hardwired to zero), and v1 is used for predicate
  58   masks.  However, both can be considered INT8 vectors.
  59
  60 **Default MVL**
  61
  62 The default RVV MVL value (in absence of explicit VCFG setup) is to
  63 be MVL = 2 on RV32I machines and MVL = 4 on RV64I machines.  However,
  64 note RV32I registers can fit 4x INT8 elements.  To preserve Andes SIMD
  65 behaviour, all VOP instructions should still operate on all “unused”
  66 elements in the register, regardless of MVL.  (This is still compliant
  67 with the RVV spec, provided elements from VL..MVL-1 are set to zero).
  68 VMEM instructions however will only operate on VL elements, and so
  69 where full Andes SIMD compliance is required (without RVV forward
  70 compatibility), LW/LD and SW/SD are to be used instead of VLD and VST.
  71
  72 **Alternative register "banks" and alternative MVL**
  73
  74 A programmer can configure VCFG with any mix of these alternative
  75 configurations:
  76
  77 *  v0-v31 are all INT 16, and MVL is same as for Default MVL above
  78 *  v0-v31 are all INT 8 and MVL is 4 on RV32I and 8 on RV64I
  79 *  A lesser number of registers (less than v31) could be supported,
  80   eg. default is only v0-v29 defined.  (Accessing registers beyond
  81   maximum defined by VDCFG is to be legal, with a type of INT32 assumed.
  82   However, this is not to affect the MVL, which is to be calculated based
  83   on INT8/INT16 vectors only)
  84 *  With the above alternative configs, there can be any split between
  85 signed & unsigned.
  86
  87 The above are pure subsets of valid RVV VCFG configurations (and hence
  88 forward compatible between RVP and RVV, whilst also keeping RVP simple).
  89 Other useful element types are fixed point fraction types and small
  90 integer(4 bit to 7 bit) elements. However these are omitted for now
  91 as they aren’t currently part of RVV spec, and the intention of this
  92 proposal is to harmonise the Andes SIMD instructions into a subset of RVV.