# RISC-V 3D GPU / CPU / VPU

Creating a trustworthy processor for the world.

Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
are implying, a "dedicated exclusive GPU".  The option exists to *create*
a stand-alone GPU product (contact us if this is a product that you want).
Our primary goal is to design a **complete** all-in-one processor
(System-on-a-Chip) that happens to include libre-licensed VPU and GPU
accelerated instructions as part of the actual - main - CPU itself.

We seek investors, sponsors (whose contributions thanks to NLNet may be
tax-deductible), engineers and potential customers, who are
interested, as a first product, in the creation and use of an entirely
libre low-power mobile class system-on-a-chip.  Comparative benchmark
performance, pincount and price is the Allwinner A64, except that the
power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
FBGA package.  Instead of single-issue higher clock rate, the design is
multi-issue, aiming for around 800mhz.

The lower pincount, lower power, and higher BGA pitch is all to reduce
the cost of product development when it comes to PCB design and layout:

* Above 4 watts requires metal packages, greater attention to thermal
  management in the PCB design and layout, and much pricier PMICs.
* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
  equipment and more costly PCBA techniques.
* Above 600 pins begins to reduce production yields as well as increase
  the cost of testing and packaging.

We can look at larger higher-power ASICs either later or, if funding
is made available, immediately.

Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
64 bit, single core dual issue, around 300 to 350mhz.  This will provide
the confidence to go to higher geometries, as well as be a commercially
viable embedded product in its own right.

# Business Objectives

See [[3d_gpu/business_objectives]]

# Links:

* [[shakti/m_class/libre_3d_gpu]]
* [[discussion]]
* [[resources]]
* [[overview]]
* [[3d_gpu/funding]]
* [[3d_gpu/architecture]]
* Founding [[charter]]
* Mailing list <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
* Crowdsupply page <https://www.crowdsupply.com/libre-risc-v/m-class>
* Wiki <https://libre-riscv.org>
* Git repositories <https://git.libre-riscv.org>
* Bugtracker <http://bugs.libre-riscv.org>
* Kazan Vulkan Driver (including 3D engine) <https://salsa.debian.org/Kazan-team/kazan>
* [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
* NLNet Project Page <https://nlnet.nl/project/Libre-RISCV/>
* [[nlnet_proposals]]
* [[llvm]]

# Progress:

* Jan 2020: New team members, Yehowshua and Michael.  Last-minute attendance of FOSDEM2020
* Dec 2019: Second round NLNet questions answered.  External Review completed.  6 NLNet proposals accepted (EUR 200,000+)
* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
* Oct 2019: 3D Standards continued.  POWER ISA considered.  Open 3D Alliance begins.  NLNet funding applications submitted.
* Sep 2019: 3D Standards continued.  Additional NLNet Funding proposals discussed.
* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
* Jul 2019: Sponsorship from Purism received.  IEEE754 FP Mul, Add, DIV,
  FCLASS and FCVT pipelines completed.
* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
* May 2019: 6600-style scoreboard started
* Apr 2019: NLnet funding approved by independent review committee
* Mar 2019: NLnet funding application first and second phase passed
* Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
* Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
* Jan 2019: Second version Simple-V preliminary proposal (suited to LLVM)
* 2017 - Nov 2018: Simple-V specification preliminary draft completed
* Aug 2018 - Nov 2018: spike-sv implementation of draft spec completed
* Aug 2018: Kazan Vulkan Driver initiated
* Sep 2018: mailing list established
* Sep 2018: Crowdsupply pre-launch page up (for updates)
* Dec 2018: preliminary floorplan and architecture designed (comp.arch)

# News Articles

* <https://www.phoronix.com/forums/forum/hardware/processors-memory/1133806-libre-risc-v-open-source-effort-now-looking-at-power-instead-of-risc-v/page7>
* <https://hub.packtpub.com/a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
* <https://riscv.org/2018/10/packt-hub-article-a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
* <https://www.reddit.com/r/RISCV/comments/9jts9t/theres_a_new_libre_gpu_effort_building_on_riscv/>
* <https://www.linux.com/blog/2018/11/risc-v-linux-development-full-swing>
* <https://www.phoronix.com/scan.php?page=news_item&px=Libre-GPU-RISC-V-Vulkan>
* <https://www.heise.de/newsticker/meldung/Mobilprozessor-mit-freier-GPU-Libre-RISC-V-M-Class-geplant-4242802.html>
* <https://news.ycombinator.com/item?id=18094734>
* <http://www.tuxmachines.org/node/116004>
* <https://linuxfr.org/users/martoni/journaux/risc-v-est-pret-pour-le-desktop>
* <https://www.reddit.com/r/hardware/comments/9jlby1/theres_a_new_libre_gpu_effort_building_on_riscv/>
* <http://www.eevblog.com/forum/crowd-funded-projects/libre-risc-v-m-class-with-open-source-gpu-and-kazan-vulkan-driver/>
* <https://www.reddit.com/domain/libre-riscv.org/>
* <https://hardware.slashdot.org/comments.pl?sid=13447940&cid=58160868>
* <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1080755-libre-risc-v-gpu-aiming-for-2-5-watt-power-draw-continues-being-plotted/page5>
* <https://www.phoronix.com/forums/forum/hardware/processors-memory/1070828-more-details-on-the-proposed-simple-v-extension-to-risc-v-for-gpu-workloads>
* <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
* <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
* <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
* <https://news.ycombinator.com/item?id=21112341>
* <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
* <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
* <https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/15>
* Dec 2019 ProLinux <https://www.pro-linux.de/news/1/27527/comm/1/show-all-comments.html>
* Dec 2019 Phoronix <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1148553-libre-risc-v-accelerator-secures-300k-eur-in-grants-still-undecided-about-the-isa/>
* Feb 15 2020 Phoronix <https://www.phoronix.com/scan.php?page=news_item&px=OpenPOWER-ISA-EULA-Draft/>

# Information Resources and Tutorials

* <https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers>
* <https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/>
* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
* <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
* <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
* <https://chips4makers.io/blog/>
* <https://hackaday.io/project/7817-zynqberry>
* <https://wiki.f-si.org/index.php/FSiC2019>
* <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
* <https://efabless.com/design_catalog/default>
* <https://toyota-ai.ventures/>
* <https://github.com/lambdaconcept/minerva>
* <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
* <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
* <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
* <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
* <https://mshahrad.github.io/openpiton-asplos16.html>
* <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
* <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
* <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
* <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
* <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
* <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
* <https://youtu.be/o5Ihqg72T3c>
* <http://flopoco.gforge.inria.fr/>
* Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>

# Analog Simulation

* <https://github.com/Isotel/mixedsim>
* <http://www.vlsiacademy.org/open-source-cad-tools.html>
* <http://ngspice.sourceforge.net/adms.html>
* <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>

# Evaluations

* [[openpower]]