X-Git-Url: https://git.libre-soc.org/?p=libreriscv.git;a=blobdiff_plain;f=3d_gpu.mdwn;h=09854d205aa8c6c0091bc9a24bc72cd50e5ac590;hp=113493e34fc2c66b58779640da027e38c99841c6;hb=HEAD;hpb=ef50a035f0a9ca829f5a687f3094c0eb2ab442ee

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 113493e34..1defb461d 100644
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -1,4 +1,4 @@
-See architectural details [here](./architecture)
+See architectural details [here](./architecture), [[gaddie]] pitch and [[business_plan]]
 
 # Hybrid 3D GPU / CPU / VPU
 
@@ -45,7 +45,20 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
-* Oct 2020 [[80nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+* Dec 2021 first MMU unit tests pass, running microwatt mmu.bin.
+  Shows MMU and L1 D/I-Caches as functional in simulation.
+* Apr 2021 cocotb simulation of 180nm ASIC implemented. JTAG TAP
+  confirmed functional on ECP5 and simulation.  FreePDK-c4m45
+  created by <https://chips4makers.io>
+* Mar 2021 first SVP64 OpenPOWER augmented Cray-style instructions executed.
+  NGI POINTER EUR 200,000 grant submitted.
+* Feb 2021 FOSDEM2021, Simple-V SVP64 implementation starts in
+  simulator and Test Issuer
+* Jan 2021 FOSDEM2021 talks confirmed, NLnet crypto-primitives proposal
+  submitted, budget agreed for basic binutils and gcc SVP64 support
+* Dec 2020 work on [[openpower/sv/svp64]] started
+* Nov 2020 dry-run 180nm GDSII sent to IMEC
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
   for 180nm test ASIC, GDSII deadline set of Dec 2nd.
 * Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
 * Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation