From: lkcl <lkcl@web>
Date: Thu, 24 Oct 2019 01:15:37 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3847
X-Git-Url: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff_plain;h=62fa99f545d541842e5dfb36e2d02975045afb68

---

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index cc12b5a52..998e0cd68 100644
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -65,6 +65,7 @@ Progress:
 
 # News Articles
 
+* <https://www.phoronix.com/forums/forum/hardware/processors-memory/1133806-libre-risc-v-open-source-effort-now-looking-at-power-instead-of-risc-v/page7>
 * <https://hub.packtpub.com/a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
 * <https://riscv.org/2018/10/packt-hub-article-a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
 * <https://www.reddit.com/r/RISCV/comments/9jts9t/theres_a_new_libre_gpu_effort_building_on_riscv/>
@@ -125,3 +126,7 @@ Progress:
 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
 * <http://ngspice.sourceforge.net/adms.html>
 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
+
+# Evaluations
+
+*[[openpower]]