From: lkcl <lkcl@web>
Date: Wed, 17 Nov 2021 23:52:21 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3370
X-Git-Url: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff_plain;h=7dc0d6bc831e2d8cdecf6556b5a62fd9e613ce0e

---

diff --git a/shakti/m_class/UART.mdwn b/shakti/m_class/UART.mdwn
index f54f01287..66ae63023 100644
--- a/shakti/m_class/UART.mdwn
+++ b/shakti/m_class/UART.mdwn
@@ -5,4 +5,4 @@ Several pages on opencores, including:
 * <https://opencores.org/projects/uart16550> which has wishbone
 * <https://github.com/freecores/uart16550> freecores version (basically same as above)
 * <https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/heavycomps/heavycomps/uart.py>
-
+* <https://github.com/antonblanchard/lpcperipheral/blob/master/lpcperipheral/lpcfront.py>